Rainbow Electronics AT27C2048 - Manual (Page 2)

AT27C2048
2
In read mode, the AT27C2048 typically consumes 15 mA.
Standby mode supply current is typically less than 10
µ
A
.
T h e A T 2 7 C 2 0 4 8 i s a v a i l a b le i n i n d u s t ry s t a n d a r d
JEDEC-approved one-time programmable (OTP) plastic
PDIP, PLCC, and VSOP packages. The device features
two-line control (CE, OE) to eliminate bus contention in
high-speed systems.
With high density 128K word storage capability, the
AT27C2048 allows firmware to be stored reliably and to be
accessed by the system without the delays of mass storage
media.
Atmel’s AT27C2048 has additional features that ensure
high quality and efficient production use. The Rapid
™ Pro-
gramming Algorithm reduces the time required to program
the part and guarantees reliable programming. Program-
ming time is typically only 50
µ
s/word. The Integrated Prod-
uct Identification Code electronically identifies the device
and manufacturer. This feature is used by industry stan-
dard programming equipment to select the proper program-
ming algorithms and voltages.
System Considerations
Switching between active and standby conditions via the
Chip Enable pin may produce transient voltage excursions.
Unless accommodated by the system design, these tran-
sients may exceed data sheet limits, resulting in device
non-conformance. At a minimum, a 0.1 µF high frequency,
low inherent inductance, ceramic capacitor should be uti-
lized for each device. This capacitor should be connected
between the V
CC
and Ground terminals of the device, as
close to the device as possible. Additionally, to stabilize the
supply voltage level on printed circuit boards with large
EPROM arrays, a 4.7 µF bulk electrolytic capacitor should
be utilized, again connected between the V
CC
and Ground
terminals. This capacitor should be positioned as close as
possible to the point where the power supply is connected
to the array.
Block Diagram
GND
VPP
VCC DATA OUTPUTS
O0 - O15
OE, CE AND
PROGRAM LOGIC
Y DECODER
X DECODER
OUTPUT
BUFFERS
Y-GATING
CELL MATRIX
IDENTIFICATION
A0 - A17
ADDRESS
INPUTS
OE
CE