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Table 1. register map – Rainbow Electronics MAX5489 User Manual

Page 9

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MAX5487/MAX5488/MAX5489

Dual, 256-Tap, Nonvolatile, SPI-Interface,

Linear-Taper Digital Potentiometers

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9

Write-Wiper Register (Command 00)

Data written to the write-wiper registers (C1, C0 = 00)
controls the wiper positions. The 8 data bits (D7 to D0)
indicate the position of the wiper. For example, if DIN =
0000 0000, the wiper moves to the position closest to
L_. If DIN = 1111 1111, the wiper moves closest to H_.

This command writes data to the volatile RAM, leaving the
NV registers unchanged. When the device powers up,
the data stored in the NV registers transfers to the volatile
wiper register, moving the wiper to the stored position.

Write-NV Register (Command 01)

This command (C1, C0 = 01) stores the position of the
wipers to the NV registers for use at power-up.
Alternatively, the “copy wiper register to NV register”
command can be used to store the position of the
wipers to the NV registers. Writing to the NV registers,
does not affect the position of the wipers.

Copy Wiper Register to NV Register (Command 10)

This command (C1, C0 = 10) stores the current position
of the wiper to the NV register, for use at power-up.

Table 1. Register Map

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

CLOCK EDGE

C1

C0

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

Write Wiper Register A

0

0

0

0

0

0

0

1

D7

D6

D5

D4

D3

D2

D1

D0

Write Wiper Register B

0

0

0

0

0

0

1

0

D7

D6

D5

D4

D3

D2

D1

D0

Write NV Register A

0

0

0

1

0

0

0

1

D7

D6

D5

D4

D3

D2

D1

D0

Write NV Register B

0

0

0

1

0

0

1

0

D7

D6

D5

D4

D3

D2

D1

D0

Copy Wiper Register A to NV
Register A

0

0

1

0

0

0

0

1

Copy Wiper Register B to NV
Register B

0

0

1

0

0

0

1

0

Copy Both Wiper Registers to
NV Registers

0

0

1

0

0

0

1

1

Copy NV Register A to Wiper
Register A

0

0

1

1

0

0

0

1

Copy NV Register B to Wiper
Register B

0

0

1

1

0

0

1

0

Copy Both NV Registers to
Wiper Registers

0

0

1

1

0

0

1

1

Figure 2. Timing Diagram

CS

t

CSO

t

CSS

t

CL

t

CH

t

DH

t

DS

t

CP

t

CSH

t

CSW

t

CS1

SCLK

DIN