Renesas Emulator System SH7362 - Manual (Page 58)

50
Table 2.12 Measurement Items (cont)
Classification Type Measurement Item Option Note
Operand bus
performance
(cont) Access
miss count Number of operand
cache miss (READ) CMR The number of cache misses
by an operand cache access
(read) (number of accesses to
the outside of the CPU core
due to a cache miss).
Cache misses are not counted
by the PREF instruction.
Number of operand
cache miss (WRITE) CMW The number of cache misses
by an operand cache access
(write) (number of accesses to
the outside of the CPU core
due to a cache miss).
Write-through accesses are not
counted.
Cache misses are not counted
by the PREF instruction.
Number of U-RAM
read-buffer miss UBM
Waited
cycle
Waited cycles for
operand fetch
(READ) WOR The number of wait cycles by a
memory access (read) of an
operand.
Waited cycles for
operand fetch
(WRITE) WOW The number of wait cycles by a
memory access (write) of an
operand.
Waited cycles for
operand cache miss
(READ) WCMR The number of wait cycles by
an operand cache miss (read)
(however, the number of wait
cycles of cache FIII is included
due to contention).
Waited cycles for
operand cache miss
(WRITE) WCMW The number of wait cycles by
an operand cache miss (write).
Waited cycles for I-L
access (READ) WILR The number of wait cycles by I-
L memory access (READ) of
an operand.
Waited cycles for I-L
access (WRITE) WILW The number of wait cycles by I-
L memory access (WRITE) of
an operand.