Renesas Emulator System SH7362 - Manual (Page 56)

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Table 2.12 Measurement Items (cont)
Classification Type Measurement Item Option Note
Instruction bus
performance
(cont) Instruction
(cont) Number of
instruction cache
miss ICM The number of cache misses
by an instruction cache
access (the number of
accesses to the outside of the
CPU core due to a cache
miss).
Number of internal-
RAM access for
instruction fetch
(XY-RAM or O-L
memory) XL The number of accesses for
the XY memory in the
SH7362 during memory
accesses of the opcode.
Number of I-L
memory access for
instruction fetch ILIF The number of accesses for
the I-L memory in the SH7362
during memory accesses of
the opcode.
Number of U
memory access for
instruction fetch ULF The number of accesses for
the U memory in the SH7362
during memory accesses of
the opcode.
Operand bus
performance Access
count Number of memory
access for operand
fetch (READ) MR The number of memory
accesses by an operand read
(equal to loading on the
operand bus).
Accesses by the PREF
instruction or canceled
accesses are not included.
Number of memory
access for operand
fetch (WRITE) MW The number of memory
accesses by an operand write
(equal to storing memory on
the operand bus).
Canceled accesses are not
included.
Number of operand
cache access
(READ) CR The number of operand-
cache reads during memory
access (read) of an operand.
Number of operand
cache access
(WRITE) CW The number of operand-
cache reads during memory
access (write) of an operand.