Renesas 32176 - Manual (Page 16)

32176 Group
Starter Kit User’s Manual M3A-2152
REJ10B0224-0310/Rev.3.10 Mar. 2008 Page 8 of 83
3.5 About M3T-PD32RM
The following describes precautions to be observed when using M3T-PD32RM.
3.5.1 Operating Manuals
To use M3T-PD32RM of M3A-2152G52A, see the manuals shown below.
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M3T-PD32RM release notes
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PD32RM Help
To use M3S-KD32R of M3A-2152G52, see the manuals shown below.
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M3S-KD32R release notes
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PD32R Help
3.5.2 About Break Operation
M3T-PD32RM (or M3S-KD32R) uses the M32R core’s internal debug circuit (SDI) to realize break
functions. For this reason, the break functions of M3T-PD32RM (or M3S-KD32R) behave
differently from those in conventional emulators.
Furthermore, because M3T-PD32RM (or M3S-KD32R) does not have SDI trace pins as
corresponding hardware resources, the trace pin corresponding break functions available with
M3T-PD32R-compatible emulators are not supported.
The following explains the four types of breaks that can be executed with M3T-PD32RM (or
M3S-KD32R).
(1) Software break
Up to 64 software breakpoints can be set and executed in RAM areas accessible by the target
MCU. No software breakpoints can be set and executed in ROM areas such as the internal flash
memory.
(2) Pre-execution PC break
The M32R core’s internal debug circuit (SDI) allows setting breakpoints, at which to break the
program immediately before executing an instruction (at the address indicated by the program
counter).
For the M3A-2152G52A and M3A-2152G52 (32176 Group MCU), four such breakpoints can be
set.
(3) Post-execution PC break
The M32R core’s internal debug circuit (SDI) allows setting one breakpoint, at which to break the
program immediately after executing an instruction (at the address indicated by the program
counter).
(4) Chip break
The M32R core’s internal debug circuit (SDI) allows setting breakpoints, at which to break the
program when accessing memory for read/write.
For M3A-2152G52A and M3A-2152G52 (32176 Group MCU), two such breakpoints (level 2) can
be set.
* The differences between levels 1 and 2 are outlined below.
Level 1: Whether data which is maskable matches or not can be detected.
Level 2: Data is maskable and an address range can be specified for the target data.