LSI 53C810A - Manual (Page 96)

5-22 Operating Registers
R Reserved 1
IID Illegal Instruction Detected 0
This status bit is set any time an illegal instruction is
detected, whether the LSI53C810A is operating in
single step mode or automatically executing SCSI
SCRIPTS.
Any of the following conditions during instruction
execution also set this bit:
•
The LSI53C810A is executing a Wait Disconnect
instruction and the SCSI REQ line is asserted without
a disconnect occurring.
•
A Move, Chained Move, or Memory Move command
with a byte count of zero is fetched.
•
A Load/Store memory address maps back into chip
register space.
Register: 0x0D (0x8D)
SCSI Status Zero (SSTAT0)
Read Only
ILF SIDL Full 7
This bit is set when the SCSI Input Data Latch (SIDL)
register contains data. Data is transferred from the SCSI
bus to the SCSI Input Data Latch register before being
sent to the DMA FIFO and then to the host bus. The
SCSI Input Data Latch (SIDL) register contains SCSI
data received asynchronously. Synchronous data
received does not flow through this register.
ORF SODR Full 6
This bit is set when the SCSI Output Data Register
(SODR, a hidden buffer register which is not accessible)
contains data. The SODR register is used by the SCSI
logic as a second storage register when sending data
synchronously. It is not readable or writable by the user.
It is possible to use this bit to determine how many bytes
reside in the chip when an error occurs.
7 6 5 4 3 2 1 0
ILF ORF OLF AIP LOA WOA RST/ SDP/
0 0 0 0 0 0 0 0