LSI 53C810A - Manual (Page 230)

IX-8 Index
Storage Device Management System (SDMS) 2-3
STR bit 5-64
STW bit 5-65
SXFER register 5-12
synchronous clock conversion factor bits 5-9
synchronous data transfer rate 2-13
synchronous operation 2-13
SZM bit 5-62
T
target mode
SATN/ active 5-51
target mode bit 5-5
target ready 4-7
TE bit 5-63
TEMP register 5-33
temporary register 5-33
TEOP bit 5-31
termination 2-11
testability 1-6
timer test mode bit 5-64
timing diagrams 7-12
PCI interface 7-26
SCSI timings 7-27
timings
PCI 7-26
SCSI 7-27
TolerANT 1-2
enable bit 5-63
extend SREQ/SACK filtering bit 5-63
totem pole output 4-3
TP[2:0] bits 5-12
transfer control instructions 6-27
prefetch unit flushing 2-4
transfer rate 1-3
clock conversion factor bits 5-10
synchronous 2-13
synchronous clock conversion factor bits 5-9
TRDY/ 4-7
TRG bit 5-5
TTM bit 5-64
TYP[3:0] bits 5-55
U
UDC bit 5-49
,
5-52
unexpected disconnect bit 5-49
,
5-52
V
VAL bit 5-19
VDD 4-3
VDD-C 4-3
VSS 4-3
VSS-C 4-3
VSS-S 4-3
W
WATN bit 5-4
WOA bit 5-23
won arbitration bit 5-23
Z
ZMOD bit 5-35
ZSD bit 5-35