Dma status (dstat), Dma status, Dstat) – LSI 53C810A User Manual
Page 94: Register: 0x0b (0x8b), Register: 0x0c (0x8c)
5-20
Operating Registers
Register: 0x0B (0x8B)
SCSI Bus Control Lines (SBCL)
Read Only
REQ
SREQ/ Status
7
ACK
SACK/ Status
6
BSY
SBSY/ Status
5
SEL
SSEL/ Status
4
ATN
SATN/ Status
3
MSG
SMSG/ Status
2
C/D
SC_D/ Status
1
I/O
SI_O/ Status
0
This register returns the SCSI control line status. A bit is set when the
corresponding SCSI control line is asserted. These bits are not latched;
they are a true representation of what is on the SCSI bus at the time the
register is read. The resulting read data is synchronized before being
presented to the PCI bus to prevent parity errors from being passed to
the system. This register is used for diagnostics testing or operation in
low level mode.
Register: 0x0C (0x8C)
DMA Status (DSTAT)
Read Only
Reading this register clears any bits that are set at the time the register
is read, but does not necessarily clear the register in case additional
interrupts are pending (the LSI53C810A stacks interrupts). The DIP bit
7
6
5
4
3
2
1
0
REQ
ACK
BSY
SEL
ATN
MSG
C/D
I/O
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
DFE
MDPE
BF
ABRT
SSI
SIR
R
IID
1
0
0
0
0
0
x
0