Figure2.2 lsi53c810a host interface data paths, Lsi53c810a host interface data paths – LSI 53C810A User Manual
Page 30
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Functional Description
Step 2.
Read bit 7 in the
register to
determine if any bytes are left in the
register. If bit 7 is set in SSTAT0, then the
register is full.
Synchronous SCSI Receive –
Step 1.
Subtract the seven least significant bits of the
register from the 7-bit value of the
register. AND the result with 0x7F for a byte count
between zero and 80.
Step 2.
Read the
register and examine bits
[7:4], the binary representation of the number of valid bytes in
the SCSI FIFO, to determine if any bytes are left in the SCSI
FIFO.
Figure 2.2
LSI53C810A Host Interface Data Paths
PCI
DMA FIFO
(4-bytes x 20)
DMA FIFO
(4-bytes x 20)
SODL Register
SIDL Register
SCSI Interface
SCSI Interface
Asynchronous
SCSI Send
Asynchronous
SCSI Receive
DMA FIFO
(4-bytes x 20)
DMA FIFO
(4-bytes x 20)
SODR Register
SODL Register
SCSI Interface
SCSI Interface
SCSI FIFO
Synchronous
SCSI Send
Synchronous
SCSI Receive
Interface
PCI
Interface
PCI
Interface
PCI
Interface