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HighWire HW400c/2 User Reference Guide Rev 1.0
Table 48. Warm Reset Register (WRR) Offset address 0x17..................................................................... 58
Table 49. SPI Page Register (SPR) Offset Address 0x1A ......................................................................... 58
Table 50. SPI Address Register (SAR) Offset Address 0x1B ................................................................... 58
Table 51. SPI Read Byte Offset Select Register (SOR) Offset Address 0x1C .......................................... 59
Table 52. Read Byte Count Register (RBC) Offset Address 0x1D ........................................................... 59
Table 53. Write Byte Count Register (WBC) Offset Address 0x1E.......................................................... 60
Table 54. SPI Data Registers (SDRn) Offset Address 0x20-0x27............................................................. 60
Table 55. SPI Error and Status Register (SESR) Offset Address 0x1F ..................................................... 61
Table 56. EEPROM Address Register (EAR) Offset Address 0x28 ......................................................... 61
Table 57. EEPROM Operation/Status Register (EOSR) Offset Address 0x29 ......................................... 62
Table 58. EEPROM Data Registers (EDRn) Offset Address 0x2A-0x2B ................................................ 63
October 10, 2006
Copyright 2006, SBE, Inc.
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