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HighWire HW400c/2 User Reference Guide Rev 1.0
Table 14. Layer 2 Switch Port Assignments.............................................................................................. 27
Table 15. Compact PCI connector J3 pin out ............................................................................................. 30
Table 16. Mezzanine Card Power Budget ................................................................................................. 33
Table 17. PTMC/PMC Connector Summary ............................................................................................. 33
Table 18. PTMC Jn1 and Jn2 Connector Pin Assignments ....................................................................... 34
Table 19. PTMC Configuration #2/#5 Pn3 Connector Pin Assignment .................................................... 35
Table 20. PTMC Site A Configuration #2/#5 Pn4 Connector Pin Assignment ......................................... 37
Table 21. PTMC Site B Configuration #2/#5 Pn4 Connector Pin Assignment ......................................... 38
Table 22. GPIO Port Assignments for IPMI.............................................................................................. 40
Table 23. Voltage Monitor A/D Port Assignments for IPMI..................................................................... 41
Table 24. HW400c/2 Temperature Sensor Locations ................................................................................ 41
Table 25. Firmware EEPROM Addresses ................................................................................................. 42
Table 26. Product ID number..................................................................................................................... 43
Table 27. Overview of Hot Swap Insertion/Extraction Sequences............................................................ 45
Table 28. HW400c/2 Memory Map ........................................................................................................... 46
Table 29. CPLD Registers ......................................................................................................................... 47
Table 30. Clock Select Register (CSR) Offset Address 0x04.................................................................... 48
Table 31. Board Select Register (BSR) Offset Address 0x05 ................................................................... 49
Table 32. LED Register A (LEDA) Offset Address 0x06 ......................................................................... 49
Table 33. Memory Option Register (MOR) Offset Address 0x07............................................................. 50
Table 34. Geographic Addressing Register (CSR) Offset Address 0x08 .................................................. 50
Table 35. PTMC Reset Register (PRR) Offset Address 0x09 ................................................................... 51
Table 36. PTMC Control Register (PCR) Offset Address 0x0A ............................................................... 51
Table 37. Board Option Register (BOR) Offset Address 0x0D................................................................. 52
Table 38. General Purpose Register (GPR) Offset Address 0x0E............................................................. 52
Table 39. PCI Status Register (PSR) Offset Address 0x0F ....................................................................... 53
Table 40. Extended Type Register (ETR) Offset Address 0x10................................................................ 53
Table 41. Hardware Revision Register (HRR) Offset Address ................................................................. 54
Table 42. PLL Configuration Register A (PLLA) Offset Address 0x12 ................................................... 54
Table 43. PLL Configuration Register B (PLLB) Offset Address 0x13.................................................... 55
Table 44. LED Register B (LEDB) Offset Address 0x14.......................................................................... 56
Table 45. On-board LED functions as determined by LEDB [1:0] ........................................................... 56
Table 46. Device Control Register (CSR) Offset Address 0x15 ............................................................... 57
Table 47. CPU Timer Register (CTR) Offset Address 0x16 ..................................................................... 57
October 10, 2006
Copyright 2006, SBE, Inc.
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