SUPER MICRO Computer H8QI6-F - Manual (Page 62)

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H8QI6/i-F Serverboard User’s Manual
L2 Cache BG Scrub
Allows L2 cache RAM to be corrected when idle. Options are Disabled and
various times in nanoseconds and microseconds. The default is 2.56us.
L3 Cache BG Scrub
Allows L3 cache RAM to be corrected when idle. Options are Disabled and
various times in nanoseconds and microseconds. The default is 2.56us.
DRAM Timing Confi guration
Memory Clock Mode
This setting specifi es the memory clock mode. Options are Auto, Limit
and Manual.
DRAM Timing Mode
This setting specifi es the DRAM timing mode. Options are Auto and DCT0,
DCT1 and Both.
Alternate VID
Specify the alternate VID while in low power states. Options are Auto and
various voltages from .800V to 1.050V in increments of .025V.
Memory Timing Parameters
This selects the which node's timing parameters to display. Options are
CPU Node 0 or CPU Node 1.
SouthBridge Confi guration
OHCI/EHCI HC Device Functions
These settings allow you to either Enable or Disable functions for OHCI or
EHCI bus devices.
On Chip SATA Channel
This setting allows you to Enable or Disable the OnChip SATA channel.
On Chip SATA Type
Use this setting to set the On Chip SATA type. Options include
Native IDE, RAID, AHCI and Legacy IDE.