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Table 4.2 mii/rmii signal mapping, 7 auto-negotiation, Auto-negotiation – SMSC FlexPWR LAN8710i User Manual

Page 28: Datasheet

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MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR

®

Technology in a Small Footprint

Datasheet

Revision 1.0 (04-15-09)

28

SMSC LAN8710/LAN8710i

DATASHEET

Note 4.1

In RMII mode, this pin needs to tied to VSS.

Note 4.2

The RXER signal is optional on the RMII bus. This signal is required by the transceiver,
but it is optional for the MAC. The MAC can choose to ignore or not use this signal.

The RMII REF_CLK is a continuous clock that provides the timing reference for CRS_DV, RXD[1:0],
TXEN, TXD[1:0] and RXER. The LAN8710 uses REF_CLK as the network clock such that no buffering
is required on the transmit data path. However, on the receive data path, the receiver recovers the
clock from the incoming data stream, and the LAN8710 uses elasticity buffering to accommodate for
differences between the recovered clock and the local REF_CLK.

4.7

Auto-negotiation

The purpose of the Auto-negotiation function is to automatically configure the transceiver to the
optimum link parameters based on the capabilities of its link partner. Auto-negotiation is a mechanism
for exchanging configuration information between two link-partners and automatically selecting the
highest performance mode of operation supported by both sides. Auto-negotiation is fully defined in
clause 28 of the IEEE 802.3 specification.

Once auto-negotiation has completed, information about the resolved link can be passed back to the
controller via the Serial Management Interface (SMI). The results of the negotiation process are
reflected in the Speed Indication bits in register 31, as well as the Link Partner Ability Register
(Register 5).

Table 4.2 MII/RMII Signal Mapping

LAN8710 PIN NAME

MII MODE

RMII MODE

TXD0

TXD0

TXD0

TXD1

TXD1

TXD1

TXEN

TXEN

TXEN

RXER/

RXD4/PHYAD0

RXER

RXER

Note 4.2

COL/CRS_DV/MODE2

COL

CRS_DV

RXD0/MODE0

RXD0

RXD0

RXD1/MODE1

RXD1

RXD1

TXD2

TXD2

Note 4.1

TXD3

TXD3

Note 4.1

nINT/TXER/TXD4

TXER/

TXD4

CRS

CRS

RXDV RXDV

RXD2/RMIISEL

RXD2

RXD3/PHYAD2

RXD3

TXCLK

TXCLK

RXCLK/PHYAD1

RXCLK

XTAL1/CLKIN

XTAL1/CLKIN

REF_CLK

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