SMSC FlexPWR LAN8710 Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for FlexPWR LAN8710 SMSC
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 79 |
| Size: | 1.07 MB |
Show table of contents
Document Outline
- Chapter 1 Introduction
- Chapter 2 Pin Configuration
- Chapter 3 Pin Description
- Chapter 4 Architecture Details
- 4.1 Top Level Functional Architecture
- 4.2 100Base-TX Transmit
- 4.3 100Base-TX Receive
- 4.4 10Base-T Transmit
- 4.5 10Base-T Receive
- 4.6 MAC Interface
- 4.7 Auto-negotiation
- 4.8 HP Auto-MDIX Support
- 4.9 Internal +1.2V Regulator Disable
- 4.10 nINTSEL Strapping and LED Polarity Selection
- Table 4.3 Configuration
- Figure 4.5 nINTSEL Strapping on LED2
- 4.11 REGOFF and LED Polarity Selection
- 4.12 PHY Address Strapping
- 4.13 Variable Voltage I/O
- 4.14 Transceiver Management Control
- Chapter 5 SMI Register Mapping
- Table 5.1 Control Register: Register 0 (Basic)
- Table 5.2 Status Register: Register 1 (Basic)
- Table 5.3 PHY ID 1 Register: Register 2 (Extended)
- Table 5.4 PHY ID 2 Register: Register 3 (Extended)
- Table 5.5 Auto-Negotiation Advertisement: Register 4 (Extended)
- Table 5.6 Auto-Negotiation Link Partner Base Page Ability Register: Register 5 (Extended)
- Table 5.7 Auto-Negotiation Expansion Register: Register 6 (Extended)
- Table 5.8 Register 15 (Extended)
- Table 5.9 Silicon Revision Register 16: Vendor-Specific
- Table 5.10 Mode Control/ Status Register 17: Vendor-Specific
- Table 5.11 Special Modes Register 18: Vendor-Specific
- Table 5.12 Register 24: Vendor-Specific
- Table 5.13 Register 25: Vendor-Specific
- Table 5.14 Symbol Error Counter Register 26: Vendor-Specific
- Table 5.15 Special Control/Status Indications Register 27: Vendor-Specific
- Table 5.16 Special Internal Testability Control Register 28: Vendor-Specific
- Table 5.17 Interrupt Source Flags Register 29: Vendor-Specific
- Table 5.18 Interrupt Mask Register 30: Vendor-Specific
- Table 5.19 PHY Special Control/Status Register 31: Vendor-Specific
- Table 5.20 SMI Register Mapping
- 5.1 SMI Register Format
- Table 5.21 Register 0 - Basic Control
- Table 5.22 Register 1 - Basic Status
- Table 5.23 Register 2 - PHY Identifier 1
- Table 5.24 Register 3 - PHY Identifier 2
- Table 5.25 Register 4 - Auto Negotiation Advertisement
- Table 5.26 Register 5 - Auto Negotiation Link Partner Ability
- Table 5.27 Register 6 - Auto Negotiation Expansion
- Table 5.28 Register 16 - Silicon Revision
- Table 5.29 Register 17 - Mode Control/Status
- Table 5.30 Register 18 - Special Modes
- Table 5.31 Register 26 - Symbol Error Counter
- Table 5.32 Register 27 - Special Control/Status Indications
- Table 5.33 Register 28 - Special Internal Testability Controls
- Table 5.34 Register 29 - Interrupt Source Flags
- Table 5.35 Register 30 - Interrupt Mask
- Table 5.36 Register 31 - PHY Special Control/Status
- 5.2 Interrupt Management
- 5.3 Miscellaneous Functions
- Chapter 6 AC Electrical Characteristics
- 6.1 Serial Management Interface (SMI) Timing
- 6.2 MII 10/100Base-TX/RX Timings
- 6.3 RMII 10/100Base-TX/RX Timings (50MHz REF_CLK IN)
- 6.4 RMII CLKIN Requirements
- 6.5 Reset Timing
- 6.6 Clock Circuit
- Chapter 7 DC Electrical Characteristics
- Chapter 8 Application Notes
- 8.1 Application Diagram
- 8.1.1 MII Diagram
- 8.1.2 Power Supply Diagram
- Figure 8.2 High-Level System Diagram for Power
- Figure 8.3 High-Level System Diagram for Power
- 8.1.3 Twisted-Pair Interface Diagram
- Figure 8.4 Copper Interface Diagram
- Figure 8.5 Copper Interface Diagram
- 8.2 Magnetics Selection
- 8.1 Application Diagram
- Chapter 9 Package Outline