Imr — interrupt mask register – Samsung S3C8275X User Manual
Page 86
CONTROL REGISTERS
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X
4-16
IMR
— Interrupt Mask Register
DDH
Set 1
Bit Identifier
.7
.6
.5 .4 .3 .2 .1 .0
Reset Value
x x x x x x x x
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode
Register addressing mode only
.7
Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P1.4–1.7
0
Disable (mask)
1
Enable (unmask)
.6
Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P1.3
0
Disable (mask)
1
Enable (unmask)
.5
Interrupt Level 5 (IRQ5) Enable Bit; External Interrupt P0.2
0
Disable (mask)
1
Enable (unmask)
.4
Interrupt Level 4 (IRQ4) Enable Bit; External Interrupt P0.1
0
Disable (mask)
1
Enable (unmask)
.3
Interrupt Level 3 (IRQ3) Enable Bit; External Interrupt P0.0
0
Disable (mask)
1
Enable (unmask)
.2
Interrupt Level 2 (IRQ2) Enable Bit; Watch Timer Overflow
0
Disable (mask)
1
Enable (unmask)
.1
Interrupt Level 1 (IRQ1) Enable Bit; SIO Interrupt
0
Disable (mask)
1
Enable (unmask)
.0
Interrupt Level 0 (IRQ0) Enable Bit; Timer 1/A Match, Timer B Match
0
Disable (mask)
1
Enable (unmask)
NOTE: When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU.