Intel 537EX - Manual (Page 100)

100 536EX Chipset Developer’s Manual
Intel Confidential
Parallel Host Interface 16C450/16C550A UART
9.2.8 Interrupt Enable Register (IER)
This register is used to enable up to five types of UART interrupts: receiver line status, received
data available, character time-out indication (FIFO mode only), Transmitter Holding register
empty, and modem status. Each enabled interrupt can individually cause an interrupt to host on the
µP HINT output pin. To cause an interrupt to the host (HINT), both the interrupt enable bit and
OUT2 (MCR2) must be set to ‘1’.
9.2.9 Transmitter Holding Register (THR)
The THR (Transmitter Holding register) is a write-only register used for sending data and AT
commands to the modem.
Bit 3
Interrupt ID Bit 2—In 16C450 mode, this bit is always a ‘0’.
In FIFO mode, both this bit and bit IIR2 are set whenever a time-out interrupt is pending.
Bits 2:1 Interrupt ID Bits ID0 and ID1—These two bits are used to identify the highest-priority interrupt as shown in Table 28 .
Bit 0
Interrupt Pending—This bit indicates when a modem interrupt is pending. Whenever this bit is equal to ‘0’, then one
or more interrupts are pending. Whenever this bit is equal to ‘1’, then no interrupts are pending. When an interrupt has
occurred, the host can determine the cause of the interrupt by looking at the IIR interrupt ID bits 0 and 1 (and interrupt
ID bit 2 for FIFO mode).
Figure 21. Interrupt Enable Register (IER)
0 0 0 0 MSIE RLSIE THREIE RDAIE Register 1
(DLAB = 0)
Bits 7:4 Not used—These bits are permanently set to ‘0’.
Bit 3 MSIE (Modem Status Interrupt Enabled)—when set to ‘1’, this bit enables the modem status interrupt.
Bit 2 RLSIE (Receiver Line Status Interrupt Enabled)—when set to ‘1’, this bit enables the receiver line status interrupt.
Bit 1
THREIE (Transmitter Holding Register Empty Interrupt Enabled)—when set to ‘1’, this bit enables the Transmitter
Holding register empty interrupt.
Bit 0
RDAIE (Received Data Available Interrupt Enabled)—when set to ‘1’, this bit enables the received data available
interrupt.
Figure 22. Transmitter Holding Register (THR)
THR Register 0
(DLAB = 0)