MSI MS-6566 - Manual (Page 59)

Chapter 3
3-18
The set ting must be set t o En able d if any ISA bus ada pter in the syst em
requires VGA palette snooping.
PCI Slot1/6 IRQ, PCI Slot2/5 IRQ, PCI Slot3 IRQ, PCI Slot4 IRQ
This item specifies the IRQ line for each PCI slot. Settings: 3, 4, 5, 7, 9, 10, 11
and Auto. Selecting Auto allows BIOS to automatically determine the IRQ line
for each PCI slot.
DMA Channel 0/1/3/5/6/7
These items specify the bus t hat the syst em DMA (Direct Memory Access)
channel is used.
The settings determine if AMIBIOS should remove a DMA from the available
DM As p asse d to de vice s th at are configurabl e by the sy stem BIOS. The
availab le DMA pool i s determined b y reading the ESCD NVRAM. If more
DMAs must be removed from the pool, the end user can reserve the DMA by
assigning an ISA/EISA setting to it.
IRQ 3/4/5/7/9/10/11
These items specify the bus where the specified IRQ line is used.
The settings determine if AMIBIOS sh ould remove an IRQ from the pool of
available IRQs passed to devices that are configurable by the system BIOS.
The available IRQ pool is determined by reading the ESCD NVRAM. If more
IRQs must be removed from the IRQ pool, the end user can use these settings
to reserv e the IRQ by assig ning a n ISA/EIS A se tting to i t. Onboard I/O is
configured b y AMIBIOS. All IRQs use d by on board I/ O are c onfigure d as
PCI/PnP. If all IRQs are set to ISA/EISA, and IRQ 14/15 are allocated to the
onboard PCI IDE, IRQ 9 will still be available for PCI and PnP devices. Avail-
able settings: ISA/EISA and PCI/PnP.
VGA Palette Snoop
Bit Setting
Action
Disabled Data read or written by the CPU is only d irected to the
PCI VGA device’s palette registers.
Enabled Data read or written by the CPU is direct ed to both the
PCI VGA d evice ’s pal ette registers a nd th e ISA VGA
device’s palette registers, permitting the palette registers
of both VGA devices to be identical.