Maxim Integrated MAX31782 - Manual (Page 180)

MaximIntegrated 19-15
MAX31782 User’s Guide
Revision 0; 8/11
To support high priority interrupts while servicing another interrupt source, the IMR register may be used to create a
user-defined prioritization . The IMR mask register should not be utilized when the highest priority interrupt is being
serviced because the highest priority interrupt should never be interrupted . This is default condition when a hardware
branch is made the Interrupt Vector address (INS is set to 1 by hardware and all other interrupt sources are blocked) .
The code below demonstrates how to use IMR to allow other interrupts .
ISR_Z:
pop PSF ; restore PSF
push IMR ; save current interrupt mask
move IMR, #int_mask ; new mask to allow only higher priority ints move
INS, #0 ; re-enable interrupts
...
(interrupt servicing code)
...
pop
IMR ; restore previous interrupt mask
ret ; back to code or lower priority interrupt
Note that configuring a given IMR register mask bit to ‘0’ only prevents interrupt conditions from the corresponding
module or system from generating an interrupt request . Configuring an IMR mask bit to ‘0’ does not prevent the cor-
responding IIR system or module identification flag from being set . This means that when using the IMR mask register
functionality to block interrupts, there may be cases when both the mask (IMR .x) and identifier (IIR .x) bits should be
considered when determining if the corresponding peripheral should be serviced .
19.8.1ConditionalReturnfromInterrupt
Similar to the conditional returns, the MAX31782 also supports a set of conditional return from interrupt operations .
Based upon the value of one of the status flags, the CPU can conditionally pop the stack, clear the INS bit to 0, and
begin execution at the address popped from the stack . If the condition is not true, the conditional return from inter-
rupt instruction leaves the INS bit unchanged, does not pop the stack and does not change the instruction pointer . The
following conditional return from interrupt operations are supported:
RETI C ; if C=1, a RETI is executed
RETI NC ; if C=0, a RETI is executed
RETI Z ; if Z=1 (Acc=00h), a RETI is executed
RETI NZ ; if Z=0 (Acc<>00h), a RETI is executed
RETI S ; if S=1, a RETI is executed