Maxim Integrated MAX31782 - Manual (Page 101)

MaximIntegrated 11-7
MAX31782 User’s Guide
Revision 0; 8/11
11.3.3GPIOInputRegisterforPort6(PI6)
PI6 is an 8-bit register that contains the data that is applied to the GPIO pins . The PI6 input register contains valid input
data even when the pin is not operating as a GPIO . The reset value for this register is dependent on the logical states
applied to the pins . Note that each pin has a weak pullup circuit when functioning as an input and the p-channel pullup
transistor is controlled by the PO6 .n bit .
11.3.4GPIOPort6ExternalInterruptEdgeSelectRegister(EIES6)
The EIES6 register sets the interrupt edge select to trigger an interrupt on either a rising or falling edge . Setting the
IESP6_n bits to 0 triggers the corresponding interrupt on a positive edge . When these bits are set to 1, the interrupt is
on a negative edge .
11.3.5GPIOPort6ExternalInterruptFlagRegister(EIF6)
These bits are set when a negative edge (IESP6 .n = 1) or a positive edge (IESP6 .n = 0) is detected on the P6 .n pin .
Setting any of the bits to 1 generates an interrupt to the CPU if the corresponding interrupt is enabled . These bits remain
set until cleared by software or a reset . These bits must be cleared by software before exiting the interrupt service
routine or another interrupt is generated as long as the bit remains set .
11.3.6GPIOPort6ExternalInterruptEnableRegister(EIE6)
Setting any of these bits to 1 enables the corresponding external interrupt . Clearing any of the bits to 0 disables the
corresponding interrupt function .
Bit 7 6 5 4 3 2 1 0
Name PI6_7 PI6_6 — PI6_4 PI6_3 PI6_2 PI6_1 PI6_0
Reset s s 1 s s s s s
Access r r r r r r r r
Bit 7 6 5 4 3 2 1 0
Name IESP6_7 IESP6_6 — IESP6_4 IESP6_3 IESP6_2 IESP6_1 IESP6_0
Reset 0 0 0 0 0 0 0 0
Access rw rw r rw rw rw rw rw
Bit 7 6 5 4 3 2 1 0
Name IFP6_7 IFP6_6 — IFP6_4 IFP6_3 IFP6_2 IFP6_1 IFP6_0
Reset 0 0 0 0 0 0 0 0
Access rw rw r rw rw rw rw rw
Bit 7 6 5 4 3 2 1 0
Name IEP6_7 IEP6_6 — IEP6_4 IEP6_3 IEP6_2 IEP6_1 IEP6_0
Reset 0 0 0 0 0 0 0 0
Access rw rw r rw rw rw rw rw