SMSC LAN9312 Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for LAN9312 SMSC
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 458 |
| Size: | 4.49 MB |
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Document Outline
- Table of Contents
- List of Figures
- List of Tables
- Chapter 1 Preface
- Chapter 2 Introduction
- Chapter 3 Pin Description and Configuration
- 3.1 Pin Diagrams
- 3.2 Pin Descriptions
- Table 3.1 LAN Port 1 Pins
- Table 3.2 LAN Port 2 Pins
- Table 3.3 LAN Port 1 & 2 Power and Common Pins
- Table 3.4 Host Bus Interface Pins
- Table 3.5 EEPROM Pins
- Table 3.6 Dedicated Configuration Strap Pins
- Table 3.7 Miscellaneous Pins
- Table 3.8 PLL Pins
- Table 3.9 Core and I/O Power and Ground Pins
- Table 3.10 No-Connect Pins
- Chapter 4 Clocking, Resets, and Power Management
- Chapter 5 System Interrupts
- 5.1 Functional Overview
- 5.2 Interrupt Sources
- Figure 5.1 Functional Interrupt Register Hierarchy
- 5.2.1 1588 Time Stamp Interrupts
- 5.2.2 Switch Fabric Interrupts
- 5.2.3 Ethernet PHY Interrupts
- 5.2.4 GPIO Interrupts
- 5.2.5 Host MAC Interrupts
- 5.2.6 Power Management Interrupts
- 5.2.7 General Purpose Timer Interrupt
- 5.2.8 Software Interrupt
- 5.2.9 Device Ready Interrupt
- Chapter 6 Switch Fabric
- 6.1 Functional Overview
- 6.2 Switch Fabric CSRs
- 6.3 10/100 Ethernet MACs
- 6.4 Switch Engine (SWE)
- 6.4.1 MAC Address Lookup Table
- 6.4.2 Forwarding Rules
- 6.4.3 Transmit Priority Queue Selection
- 6.4.4 VLAN Support
- 6.4.5 Spanning Tree Support
- 6.4.6 Ingress Flow Metering and Coloring
- 6.4.7 Broadcast Storm Control
- 6.4.8 IPv4 IGMP / IPv6 MLD Support
- 6.4.9 Port Mirroring
- 6.4.10 Host CPU Port Special Tagging
- 6.4.11 Counters
- 6.5 Buffer Manager (BM)
- 6.6 Switch Fabric Interrupts
- Chapter 7 Ethernet PHYs
- 7.1 Functional Overview
- 7.2 Port 1 & 2 PHYs
- Figure 7.1 Port x PHY Block Diagram
- 7.2.1 100BASE-TX Transmit
- 7.2.2 100BASE-TX Receive
- 7.2.3 10BASE-T Transmit
- 7.2.4 10BASE-T Receive
- 7.2.5 PHY Auto-negotiation
- 7.2.6 HP Auto-MDIX
- 7.2.7 MII MAC Interface
- 7.2.8 PHY Management Control
- 7.2.9 PHY Power-Down Modes
- 7.2.10 PHY Resets
- 7.2.11 LEDs
- 7.2.12 Required Ethernet Magnetics
- 7.3 Virtual PHY
- Chapter 8 Host Bus Interface (HBI)
- 8.1 Functional Overview
- 8.2 Host Memory Mapping
- 8.3 Host Endianess
- 8.4 Host Interface Timing
- 8.4.1 Special Situations
- 8.4.2 Special Restrictions on Back-to Back Write-Read Cycles
- 8.4.3 Special Restrictions on Back-to-Back Read Cycles
- 8.4.4 PIO Reads
- 8.4.5 PIO Burst Reads
- 8.4.6 RX Data FIFO Direct PIO Reads
- 8.4.7 RX Data FIFO Direct PIO Burst Reads
- 8.4.8 PIO Writes
- 8.4.9 TX Data FIFO Direct PIO Writes
- 8.5 HBI Interrupts
- Chapter 9 Host MAC
- 9.1 Functional Overview
- 9.2 Flow Control
- 9.3 Virtual Local Area Network (VLAN) Support
- 9.4 Address Filtering
- 9.5 Wake-up Frame Detection
- 9.6 Host MAC Address
- 9.7 FIFOs
- 9.8 TX Data Path Operation
- 9.9 RX Data Path Operation
- Chapter 10 Serial Management
- 10.1 Functional Overview
- 10.2 I2C/Microwire Master EEPROM Controller
- Table 10.1 I2C/Microwire Master Serial Management Pins Characteristics
- 10.2.1 EEPROM Controller Operation
- 10.2.2 I2C EEPROM
- 10.2.3 Microwire EEPROM
- 10.2.4 EEPROM Loader
- Chapter 11 IEEE 1588 Hardware Time Stamp Unit
- Chapter 12 General Purpose Timer & Free-Running Clock
- Chapter 13 GPIO/LED Controller
- Chapter 14 Register Descriptions
- Figure 14.1 LAN9312 Base Register Memory Map
- 14.1 TX/RX FIFO Ports
- 14.2 System Control and Status Registers
- Table 14.1 System Control and Status Registers
- 14.2.1 Interrupts
- 14.2.2 Host MAC & FIFO’s
- 14.2.2.1 Receive Configuration Register (RX_CFG)
- 14.2.2.2 Transmit Configuration Register (TX_CFG)
- 14.2.2.3 Receive Datapath Control Register (RX_DP_CTRL)
- 14.2.2.4 RX FIFO Information Register (RX_FIFO_INF)
- 14.2.2.5 TX FIFO Information Register (TX_FIFO_INF)
- 14.2.2.6 Host MAC RX Dropped Frames Counter Register (RX_DROP)
- 14.2.2.7 Host MAC CSR Interface Command Register (MAC_CSR_CMD)
- 14.2.2.8 Host MAC CSR Interface Data Register (MAC_CSR_DATA)
- 14.2.2.9 Host MAC Automatic Flow Control Configuration Register (AFC_CFG)
- 14.2.3 GPIO/LED
- 14.2.4 EEPROM
- 14.2.5 IEEE 1588
- 14.2.5.1 Port x 1588 Clock High-DWORD Receive Capture Register (1588_CLOCK_HI_RX_CAPTURE_x)
- 14.2.5.2 Port x 1588 Clock Low-DWORD Receive Capture Register (1588_CLOCK_LO_RX_CAPTURE_x)
- 14.2.5.3 Port x 1588 Sequence ID, Source UUID High-WORD Receive Capture Register (1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_x)
- 14.2.5.4 Port x 1588 Source UUID Low-DWORD Receive Capture Register (1588_SRC_UUID_LO_RX_CAPTURE_x)
- 14.2.5.5 Port x 1588 Clock High-DWORD Transmit Capture Register (1588_CLOCK_HI_TX_CAPTURE_x)
- 14.2.5.6 Port x 1588 Clock Low-DWORD Transmit Capture Register (1588_CLOCK_LO_TX_CAPTURE_x)
- 14.2.5.7 Port x 1588 Sequence ID, Source UUID High-WORD Transmit Capture Register (1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_x)
- 14.2.5.8 Port x 1588 Source UUID Low-DWORD Transmit Capture Register (1588_SRC_UUID_LO_TX_CAPTURE_x)
- 14.2.5.9 GPIO 8 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_8)
- 14.2.5.10 GPIO 8 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_8)
- 14.2.5.11 GPIO 9 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_9)
- 14.2.5.12 GPIO 9 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_9)
- 14.2.5.13 1588 Clock High-DWORD Register (1588_CLOCK_HI)
- 14.2.5.14 1588 Clock Low-DWORD Register (1588_CLOCK_LO)
- 14.2.5.15 1588 Clock Addend Register (1588_CLOCK_ADDEND)
- 14.2.5.16 1588 Clock Target High-DWORD Register (1588_CLOCK_TARGET_HI)
- 14.2.5.17 1588 Clock Target Low-DWORD Register (1588_CLOCK_TARGET_LO)
- 14.2.5.18 1588 Clock Target Reload High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI)
- 14.2.5.19 1588 Clock Target Reload/Add Low-DWORD Register (1588_CLOCK_TARGET_RELOAD_LO)
- 14.2.5.20 1588 Auxiliary MAC Address High-WORD Register (1588_AUX_MAC_HI)
- 14.2.5.21 1588 Auxiliary MAC Address Low-DWORD Register (1588_AUX_MAC_LO)
- 14.2.5.22 1588 Configuration Register (1588_CONFIG)
- 14.2.5.23 1588 Interrupt Status and Enable Register (1588_INT_STS_EN)
- 14.2.5.24 1588 Command Register (1588_CMD)
- 14.2.6 Switch Fabric
- 14.2.6.1 Port 1 Manual Flow Control Register (MANUAL_FC_1)
- 14.2.6.2 Port 2 Manual Flow Control Register (MANUAL_FC_2)
- 14.2.6.3 Port 0(Host MAC) Manual Flow Control Register (MANUAL_FC_MII)
- 14.2.6.4 Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA)
- 14.2.6.5 Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD)
- 14.2.6.6 Switch Fabric MAC Address High Register (SWITCH_MAC_ADDRH)
- 14.2.6.7 Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL)
- 14.2.6.8 Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA)
- 14.2.7 PHY Management Interface (PMI)
- 14.2.8 Virtual PHY
- Table 14.4 Virtual PHY MII Serially Adressable Register Index
- 14.2.8.1 Virtual PHY Basic Control Register (VPHY_BASIC_CTRL)
- 14.2.8.2 Virtual PHY Basic Status Register (VPHY_BASIC_STATUS)
- 14.2.8.3 Virtual PHY Identification MSB Register (VPHY_ID_MSB)
- 14.2.8.4 Virtual PHY Identification LSB Register (VPHY_ID_LSB)
- 14.2.8.5 Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV)
- 14.2.8.6 Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY)
- 14.2.8.7 Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP)
- 14.2.8.8 Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS)
- 14.2.9 Miscellaneous
- 14.2.9.1 Chip ID and Revision (ID_REV)
- 14.2.9.2 Byte Order Test Register (BYTE_TEST)
- 14.2.9.3 Hardware Configuration Register (HW_CFG)
- 14.2.9.4 Power Management Control Register (PMT_CTRL)
- 14.2.9.5 General Purpose Timer Configuration Register (GPT_CFG)
- 14.2.9.6 General Purpose Timer Count Register (GPT_CNT)
- 14.2.9.7 Free Running 25MHz Counter Register (FREE_RUN)
- 14.2.9.8 Reset Control Register (RESET_CTL)
- 14.3 Host MAC Control and Status Registers
- Table 14.6 Host MAC Adressable Registers
- 14.3.1 Host MAC Control Register (HMAC_CR)
- 14.3.2 Host MAC Address High Register (HMAC_ADDRH)
- 14.3.3 Host MAC Address Low Register (HMAC_ADDRL)
- 14.3.4 Host MAC Multicast Hash Table High Register (HMAC_HASHH)
- 14.3.5 Host MAC Multicast Hash Table Low Register (HMAC_HASHL)
- 14.3.6 Host MAC MII Access Register (HMAC_MII_ACC)
- 14.3.7 Host MAC MII Data Register (HMAC_MII_DATA)
- 14.3.8 Host MAC Flow Control Register (HMAC_FLOW)
- 14.3.9 Host MAC VLAN1 Tag Register (HMAC_VLAN1)
- 14.3.10 Host MAC VLAN2 Tag Register (HMAC_VLAN2)
- 14.3.11 Host MAC Wake-up Frame Filter Register (HMAC_WUFF)
- 14.3.12 Host MAC Wake-up Control and Status Register (HMAC_WUCSR)
- 14.4 Ethernet PHY Control and Status Registers
- 14.4.1 Virtual PHY Registers
- 14.4.2 Port 1 & 2 PHY Registers
- Table 14.7 Port 1 & 2 PHY MII Serially Adressable Registers
- 14.4.2.1 Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)
- 14.4.2.2 Port x PHY Basic Status Register (PHY_BASIC_STATUS_x)
- 14.4.2.3 Port x PHY Identification MSB Register (PHY_ID_MSB_x)
- 14.4.2.4 Port x PHY Identification LSB Register (PHY_ID_LSB_x)
- 14.4.2.5 Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)
- 14.4.2.6 Port x PHY Auto-Negotiation Link Partner Base Page Ability Register (PHY_AN_LP_BASE_ABILITY_x)
- 14.4.2.7 Port x PHY Auto-Negotiation Expansion Register (PHY_AN_EXP_x)
- 14.4.2.8 Port x PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x)
- 14.4.2.9 Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)
- 14.4.2.10 Port x PHY Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x)
- 14.4.2.11 Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x)
- 14.4.2.12 Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x)
- 14.4.2.13 Port x PHY Special Control/Status Register (PHY_SPECIAL_CONTROL_STATUS_x)
- 14.5 Switch Fabric Control and Status Registers
- Table 14.12 Indirectly Accessible Switch Control and Status Registers
- 14.5.1 General Switch CSRs
- 14.5.2 Switch Port 0, Port 1, and Port 2 CSRs
- 14.5.2.1 Port x MAC Version ID Register (MAC_VER_ID_x)
- 14.5.2.2 Port x MAC Receive Configuration Register (MAC_RX_CFG_x)
- 14.5.2.3 Port x MAC Receive Undersize Count Register (MAC_RX_UNDSZE_CNT_x)
- 14.5.2.4 Port x MAC Receive 64 Byte Count Register (MAC_RX_64_CNT_x)
- 14.5.2.5 Port x MAC Receive 65 to 127 Byte Count Register (MAC_RX_65_TO_127_CNT_x)
- 14.5.2.6 Port x MAC Receive 128 to 255 Byte Count Register (MAC_RX_128_TO_255_CNT_x)
- 14.5.2.7 Port x MAC Receive 256 to 511 Byte Count Register (MAC_RX_256_TO_511_CNT_x)
- 14.5.2.8 Port x MAC Receive 512 to 1023 Byte Count Register (MAC_RX_512_TO_1023_CNT_x)
- 14.5.2.9 Port x MAC Receive 1024 to Max Byte Count Register (MAC_RX_1024_TO_MAX_CNT_x)
- 14.5.2.10 Port x MAC Receive Oversize Count Register (MAC_RX_OVRSZE_CNT_x)
- 14.5.2.11 Port x MAC Receive OK Count Register (MAC_RX_PKTOK_CNT_x)
- 14.5.2.12 Port x MAC Receive CRC Error Count Register (MAC_RX_CRCERR_CNT_x)
- 14.5.2.13 Port x MAC Receive Multicast Count Register (MAC_RX_MULCST_CNT_x)
- 14.5.2.14 Port x MAC Receive Broadcast Count Register (MAC_RX_BRDCST_CNT_x)
- 14.5.2.15 Port x MAC Receive Pause Frame Count Register (MAC_RX_PAUSE_CNT_x)
- 14.5.2.16 Port x MAC Receive Fragment Error Count Register (MAC_RX_FRAG_CNT_x)
- 14.5.2.17 Port x MAC Receive Jabber Error Count Register (MAC_RX_JABB_CNT_x)
- 14.5.2.18 Port x MAC Receive Alignment Error Count Register (MAC_RX_ALIGN_CNT_x)
- 14.5.2.19 Port x MAC Receive Packet Length Count Register (MAC_RX_PKTLEN_CNT_x)
- 14.5.2.20 Port x MAC Receive Good Packet Length Count Register (MAC_RX_GOODPKTLEN_CNT_x)
- 14.5.2.21 Port x MAC Receive Symbol Error Count Register (MAC_RX_SYMBOL_CNT_x)
- 14.5.2.22 Port x MAC Receive Control Frame Count Register (MAC_RX_CTLFRM_CNT_x)
- 14.5.2.23 Port x MAC Transmit Configuration Register (MAC_TX_CFG_x)
- 14.5.2.24 Port x MAC Transmit Flow Control Settings Register (MAC_TX_FC_SETTINGS_x)
- 14.5.2.25 Port x MAC Transmit Deferred Count Register (MAC_TX_DEFER_CNT_x)
- 14.5.2.26 Port x MAC Transmit Pause Count Register (MAC_TX_PAUSE_CNT_x)
- 14.5.2.27 Port x MAC Transmit OK Count Register (MAC_TX_PKTOK_CNT_x)
- 14.5.2.28 Port x MAC Transmit 64 Byte Count Register (MAC_TX_64_CNT_x)
- 14.5.2.29 Port x MAC Transmit 65 to 127 Byte Count Register (MAC_TX_65_TO_127_CNT_x)
- 14.5.2.30 Port x MAC Transmit 128 to 255 Byte Count Register (MAC_TX_128_TO_255_CNT_x)
- 14.5.2.31 Port x MAC Transmit 256 to 511 Byte Count Register (MAC_TX_256_TO_511_CNT_x)
- 14.5.2.32 Port x MAC Transmit 512 to 1023 Byte Count Register (MAC_TX_512_TO_1023_CNT_x)
- 14.5.2.33 Port x MAC Transmit 1024 to Max Byte Count Register (MAC_TX_1024_TO_MAX_CNT_x)
- 14.5.2.34 Port x MAC Transmit Undersize Count Register (MAC_TX_UNDSZE_CNT_x)
- 14.5.2.35 Port x MAC Transmit Packet Length Count Register (MAC_TX_PKTLEN_CNT_x)
- 14.5.2.36 Port x MAC Transmit Broadcast Count Register (MAC_TX_BRDCST_CNT_x)
- 14.5.2.37 Port x MAC Transmit Multicast Count Register (MAC_TX_MULCST_CNT_x)
- 14.5.2.38 Port x MAC Transmit Late Collision Count Register (MAC_TX_LATECOL_CNT_x)
- 14.5.2.39 Port x MAC Transmit Excessive Collision Count Register (MAC_TX_EXCCOL_CNT_x)
- 14.5.2.40 Port x MAC Transmit Single Collision Count Register (MAC_TX_SNGLECOL_CNT_x)
- 14.5.2.41 Port x MAC Transmit Multiple Collision Count Register (MAC_TX_MULTICOL_CNT_x)
- 14.5.2.42 Port x MAC Transmit Total Collision Count Register (MAC_TX_TOTALCOL_CNT_x)
- 14.5.2.43 Port x MAC Interrupt Mask Register (MAC_IMR_x)
- 14.5.2.44 Port x MAC Interrupt Pending Register (MAC_IPR_x)
- 14.5.3 Switch Engine CSRs
- 14.5.3.1 Switch Engine ALR Command Register (SWE_ALR_CMD)
- 14.5.3.2 Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0)
- 14.5.3.3 Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1)
- 14.5.3.4 Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0)
- 14.5.3.5 Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1)
- 14.5.3.6 Switch Engine ALR Command Status Register (SWE_ALR_CMD_STS)
- 14.5.3.7 Switch Engine ALR Configuration Register (SWE_ALR_CFG)
- 14.5.3.8 Switch Engine VLAN Command Register (SWE_VLAN_CMD)
- 14.5.3.9 Switch Engine VLAN Write Data Register (SWE_VLAN_WR_DATA)
- 14.5.3.10 Switch Engine VLAN Read Data Register (SWE_VLAN_RD_DATA)
- 14.5.3.11 Switch Engine VLAN Command Status Register (SWE_VLAN_CMD_STS)
- 14.5.3.12 Switch Engine DIFFSERV Table Command Register (SWE_DIFFSERV_TBL_CFG)
- 14.5.3.13 Switch Engine DIFFSERV Table Write Data Register (SWE_DIFFSERV_TBL_WR_DATA)
- 14.5.3.14 Switch Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA)
- 14.5.3.15 Switch Engine DIFFSERV Table Command Status Register (SWE_DIFFSERV_TBL_CMD_STS)
- 14.5.3.16 Switch Engine Global Ingress Configuration Register (SWE_GLOBAL_INGRSS_CFG)
- 14.5.3.17 Switch Engine Port Ingress Configuration Register (SWE_PORT_INGRSS_CFG)
- 14.5.3.18 Switch Engine Admit Only VLAN Register (SWE_ADMT_ONLY_VLAN)
- 14.5.3.19 Switch Engine Port State Register (SWE_PORT_STATE)
- 14.5.3.20 Switch Engine Priority to Queue Register (SWE_PRI_TO_QUE)
- 14.5.3.21 Switch Engine Port Mirroring Register (SWE_PORT_MIRROR)
- 14.5.3.22 Switch Engine Ingress Port Type Register (SWE_INGRSS_PORT_TYP)
- 14.5.3.23 Switch Engine Broadcast Throttling Register (SWE_BCST_THROT)
- 14.5.3.24 Switch Engine Admit Non Member Register (SWE_ADMT_N_MEMBER)
- 14.5.3.25 Switch Engine Ingress Rate Configuration Register (SWE_INGRSS_RATE_CFG)
- 14.5.3.26 Switch Engine Ingress Rate Command Register (SWE_INGRSS_RATE_CMD)
- 14.5.3.27 Switch Engine Ingress Rate Command Status Register (SWE_INGRSS_RATE_CMD_STS)
- 14.5.3.28 Switch Engine Ingress Rate Write Data Register (SWE_INGRSS_RATE_WR_DATA)
- 14.5.3.29 Switch Engine Ingress Rate Read Data Register (SWE_INGRSS_RATE_RD_DATA)
- 14.5.3.30 Switch Engine Port 0 Ingress Filtered Count Register (SWE_FILTERED_CNT_MII)
- 14.5.3.31 Switch Engine Port 1 Ingress Filtered Count Register (SWE_FILTERED_CNT_1)
- 14.5.3.32 Switch Engine Port 2 Ingress Filtered Count Register (SWE_FILTERED_CNT_2)
- 14.5.3.33 Switch Engine Port 0 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_MII)
- 14.5.3.34 Switch Engine Port 1 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_1)
- 14.5.3.35 Switch Engine Port 2 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_2)
- 14.5.3.36 Switch Engine Port 0 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_MII)
- 14.5.3.37 Switch Engine Port 1 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_1)
- 14.5.3.38 Switch Engine Port 2 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_2)
- 14.5.3.39 Switch Engine Interrupt Mask Register (SWE_IMR)
- 14.5.3.40 Switch Engine Interrupt Pending Register (SWE_IPR)
- 14.5.4 Buffer Manager CSRs
- 14.5.4.1 Buffer Manager Configuration Register (BM_CFG)
- 14.5.4.2 Buffer Manager Drop Level Register (BM_DROP_LVL)
- 14.5.4.3 Buffer Manager Flow Control Pause Level Register (BM_FC_PAUSE_LVL)
- 14.5.4.4 Buffer Manager Flow Control Resume Level Register (BM_FC_RESUME_LVL)
- 14.5.4.5 Buffer Manager Broadcast Buffer Level Register (BM_BCST_LVL)
- 14.5.4.6 Buffer Manager Port 0 Drop Count Register (BM_DRP_CNT_SRC_MII)
- 14.5.4.7 Buffer Manager Port 1 Drop Count Register (BM_DRP_CNT_SRC_1)
- 14.5.4.8 Buffer Manager Port 2 Drop Count Register (BM_DRP_CNT_SRC_2)
- 14.5.4.9 Buffer Manager Reset Status Register (BM_RST_STS)
- 14.5.4.10 Buffer Manager Random Discard Table Command Register (BM_RNDM_DSCRD_TBL_CMD)
- 14.5.4.11 Buffer Manager Random Discard Table Write Data Register (BM_RNDM_DSCRD_TBL_WDATA)
- 14.5.4.12 Buffer Manager Random Discard Table Read Data Register (BM_RNDM_DSCRD_TBL_RDATA)
- 14.5.4.13 Buffer Manager Egress Port Type Register (BM_EGRSS_PORT_TYPE)
- 14.5.4.14 Buffer Manager Port 0 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_00_01)
- 14.5.4.15 Buffer Manager Port 0 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_02_03)
- 14.5.4.16 Buffer Manager Port 1 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_10_11)
- 14.5.4.17 Buffer Manager Port 1 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_12_13)
- 14.5.4.18 Buffer Manager Port 2 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_20_21)
- 14.5.4.19 Buffer Manager Port 2 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_22_23)
- 14.5.4.20 Buffer Manager Port 0 Default VLAN ID and Priority Register (BM_VLAN_MII)
- 14.5.4.21 Buffer Manager Port 1 Default VLAN ID and Priority Register (BM_VLAN_1)
- 14.5.4.22 Buffer Manager Port 2 Default VLAN ID and Priority Register (BM_VLAN_2)
- 14.5.4.23 Buffer Manager Port 0 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_MII)
- 14.5.4.24 Buffer Manager Port 1 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_1)
- 14.5.4.25 Buffer Manager Port 2 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_2)
- 14.5.4.26 Buffer Manager Interrupt Mask Register (BM_IMR)
- 14.5.4.27 Buffer Manager Interrupt Pending Register (BM_IPR)
- Chapter 15 Operational Characteristics
- 15.1 Absolute Maximum Ratings*
- 15.2 Operating Conditions**
- 15.3 Power Consumption
- 15.4 DC Specifications
- 15.5 AC Specifications
- 15.5.1 Equivalent Test Load
- 15.5.2 Reset and Configuration Strap Timing
- 15.5.3 Power-On Configuration Strap Valid Timing
- 15.5.4 PIO Read Cycle Timing
- 15.5.5 PIO Burst Read Cycle Timing
- 15.5.6 RX Data FIFO Direct PIO Read Cycle Timing
- 15.5.7 RX Data FIFO Direct PIO Burst Read Cycle Timing
- 15.5.8 PIO Write Cycle Timing
- 15.5.9 TX Data FIFO Direct PIO Write Cycle Timing
- 15.5.10 Microwire Timing
- 15.6 Clock Circuit
- Chapter 16 Package Outlines
- Chapter 17 Revision History