Section 14.5.2.15, Datasheet – SMSC LAN9312 User Manual

Page 336

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Revision 1.4 (08-19-08)

336

SMSC LAN9312

DATASHEET

14.5.2.15

Port x MAC Receive Pause Frame Count Register (MAC_RX_PAUSE_CNT_x)

This register provides a counter of valid received pause frame packets. The counter is cleared upon
being read.

Note:

A bad packet is one that has a FCS or Symbol error.

Port0: 041Ch

Size:

32 bits

Port1: 081Ch
Port2: 0C1Ch

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

RX Pause Frame
Count of valid packets (proper length and free of errors) that have a type
field of 8808h and an op-code of 0001(Pause).

Note:

This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.

00000000h