SMSC LAN9312 - Manual (Page 413)

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312 413 Revision 1.4 (08-19-08)
DATASHEET
14.5.4.3 Buffer Manager Flow Control Pause Level Register (BM_FC_PAUSE_LVL)
This register configures the buffer usage level when a Pause frame or backpressure is sent.
Register #: 1C02h Size: 32 bits
BITS DESCRIPTION TYPE DEFAULT
31:16 RESERVED RO -
15:8 Pause Level Low
These bits specify the buffer usage level during times when 2 or 3 ports are
active.
Each buffer is 128 bytes.
Note: A port is “active” when 36 buffers are in use for that port.
R/W 21h
7:0 Pause Level High
These bits specify the buffer usage level during times when 1 port is active.
Each buffer is 128 bytes.
Note: A port is “active” when 36 buffers are in use for that port.
R/W 3Ch