Intel 82555 Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for 82555 Intel
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 58 |
| Size: | 864 KB |
Show table of contents
Document Outline
- 1.0 Introduction
- 2.0 Architectural Overview
- 3.0 Pin Definitions
- 4.0 100BASE-TX Adapter Mode Operation
- 5.0 10BASE-T Functionality in Adapter Mode
- 6.0 Repeater Mode
- 7.0 Management Data Interface
- 7.1 MDI Frame Structure
- 7.2 MDI Registers
- 7.2.1 MDI Registers 0 - 7
- 7.2.1.1 Register 0: Control Register Bit Definitions
- 7.2.1.2 Register 1: Status Register Bit Definitions
- 7.2.1.3 Register 2: 82555 Identifier Register Bit Definitions
- 7.2.1.4 Register 3: 82555 Identifier Register Bit Definitions
- 7.2.1.5 Register 4: Auto-Negotiation Advertisement Register Bit Definitions
- 7.2.1.6 Register 5: Auto-Negotiation Link Partner Ability Register Bit Definitions
- 7.2.1.7 Register 6: Auto-Negotiation Expansion Register Bit Definitions
- 7.2.2 MDI Registers 8 - 15
- 7.2.3 MDI Registers 16 - 31
- 7.2.3.1 Register 16: 82555 Status and Control Register Bit Definitions
- 7.2.3.2 Register 17: 82555 Special Control Bit Definitions
- 7.2.3.3 Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions
- 7.2.3.4 Register 21: 100BASE-TX Receive Error Frame Counter Bit Definitions
- 7.2.3.5 Register 22: Receive Symbol Error Counter Bit Definitions
- 7.2.3.6 Register 23: 100BASE-TX Receive Premature End of Frame Error Counter Bit Definitions
- 7.2.3.7 Register 24: 10BASE-T Receive End of Frame Error Counter Bit Definitions
- 7.2.3.8 Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions
- 7.2.3.9 Register 27: 82555 Special Control Bit Definitions
- 7.2.1 MDI Registers 0 - 7
- 8.0 Auto-Negotiation Functionality
- 9.0 LED Descriptions
- 10.0 Reset and Miscellaneous Test Modes
- 11.0 Electrical Specifications and Timing Parameters
- 11.1 Absolute Maximum Ratings
- 11.2 General Operating Conditions
- 11.3 DC Characteristics
- 11.4 AC Characteristics
- Figure 13. AC Testing Level Conditions
- 11.4.1 MII Clock Specifications
- 11.4.2 MII Timing Parameters
- 11.4.3 Repeater Mode Timing Parameters
- 11.4.4 Transmit Packet Timing Parameters
- 11.4.5 Squelch Test Timing Parameters
- 11.4.6 Jabber Timing Parameters
- 11.4.7 Receive Packet Timing Parameters
- 11.4.8 10BASE-T Normal Link Pulse (NLP) Timing Parameters
- 11.4.9 Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters
- 11.4.10 Reset Timing Parameters
- 11.4.11 X1 Clock Specifications
- 11.4.12 100BASE-TX Transmitter AC Specification
- 12.0 82555 Package Information