Intel 82555 - Manual (Page 46)

82555 — Networking Silicon
42 Datasheet
The TOUT pin is controlled by different sources according to the active test instruction. The TOUT
signal is activated by the falling edge of TCK. The TAP must be reset during power-up. Otherwise,
the 82555 can wake-up during high-Z mode or NAND Test, which can be harmful to the board.
The TAP should be reset only with a hardware reset input pin and not with software reset. The
TOUT control logic selects the TISR output in all tests, except burn-in test modes.
Table 6. Test Instruction Coding
Number Code Test Instruction Select Input to TOUT
1 00000 Idle TISR D4out
2 00001 Reserved TISR D4out
3 00010 High-Z High-Z
4 00011 NAND Test TISR D4out