Intel 82555 User Manual
Product features, Datasheet, Networking silicon

82555 10/100 Mbps LAN Physical Layer
Interface
Networking Silicon
Datasheet
Product Features
■
Optimal integration for lower cost solutions
— Integrated 10/100 Mbps single chip
physical layer interface solution
— Complete 10/100 Mbps MII compliance
with MDI support
— Full duplex operation in 10 Mbps and
100 Mbps modes
— IEEE 802.3u Auto-Negotiation support
for 10BASE-T half and full duplex,
100BASE-TX half and full duplex, and
100BASE-T4 configurations
— Parallel detection algorithm for legacy
support of non-Auto-Negotiation
enabled link partner
— Integrated 10BASE-T transceiver with
built in transmit and receive filters
— Glueless interface to T4-PHY for
combination TX/T4 designs with single
magnetics
— Glueless support for 4 LEDs: activity,
link, speed, and duplex
— LED function mapping support via MDI
— Low external component count
— Single 25 MHz clock support for 10
Mbps and 100 Mbps (crystal or
oscillator)
— Single magnetics for 10 Mbps and 100
Mbps operation
— QFP 100-pin package
■
Performance enhancements
— Flow control support for IEEE 802.3x
Auto-Negotiation and Bay Technologies
PHY Base* scheme
— Adaptive Channel Equalizer for greater
functionality over varying cable lengths
— High tolerance to extreme noise
conditions
— Very low emissions
— Jabber control circuitry to prevent data
loss in 10 Mbps operation
— Auto-polarity correction for 10BASE-T
— Software compatible with 82557 drivers
■
Repeater functionality
— Repeater mode operation
— Support for forced speed of 10 Mbps
and 100 Mbps
— Automatic carrier disconnect for IEEE
802.3u compliance
— Auto-Negotiation enable/disable
capability
— Receive port enable function
— Support for 32 configurable addresses
— Narrow analog side (14 mm) for tight
packing in repeater and switch designs
Document Number: 666252-004
Revision 2.0
March 1998
Notice:
Notice:
Document Outline
- 1.0 Introduction
- 2.0 Architectural Overview
- 3.0 Pin Definitions
- 4.0 100BASE-TX Adapter Mode Operation
- 5.0 10BASE-T Functionality in Adapter Mode
- 6.0 Repeater Mode
- 7.0 Management Data Interface
- 7.1 MDI Frame Structure
- 7.2 MDI Registers
- 7.2.1 MDI Registers 0 - 7
- 7.2.1.1 Register 0: Control Register Bit Definitions
- 7.2.1.2 Register 1: Status Register Bit Definitions
- 7.2.1.3 Register 2: 82555 Identifier Register Bit Definitions
- 7.2.1.4 Register 3: 82555 Identifier Register Bit Definitions
- 7.2.1.5 Register 4: Auto-Negotiation Advertisement Register Bit Definitions
- 7.2.1.6 Register 5: Auto-Negotiation Link Partner Ability Register Bit Definitions
- 7.2.1.7 Register 6: Auto-Negotiation Expansion Register Bit Definitions
- 7.2.2 MDI Registers 8 - 15
- 7.2.3 MDI Registers 16 - 31
- 7.2.3.1 Register 16: 82555 Status and Control Register Bit Definitions
- 7.2.3.2 Register 17: 82555 Special Control Bit Definitions
- 7.2.3.3 Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions
- 7.2.3.4 Register 21: 100BASE-TX Receive Error Frame Counter Bit Definitions
- 7.2.3.5 Register 22: Receive Symbol Error Counter Bit Definitions
- 7.2.3.6 Register 23: 100BASE-TX Receive Premature End of Frame Error Counter Bit Definitions
- 7.2.3.7 Register 24: 10BASE-T Receive End of Frame Error Counter Bit Definitions
- 7.2.3.8 Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions
- 7.2.3.9 Register 27: 82555 Special Control Bit Definitions
- 7.2.1 MDI Registers 0 - 7
- 8.0 Auto-Negotiation Functionality
- 9.0 LED Descriptions
- 10.0 Reset and Miscellaneous Test Modes
- 11.0 Electrical Specifications and Timing Parameters
- 11.1 Absolute Maximum Ratings
- 11.2 General Operating Conditions
- 11.3 DC Characteristics
- 11.4 AC Characteristics
- Figure 13. AC Testing Level Conditions
- 11.4.1 MII Clock Specifications
- 11.4.2 MII Timing Parameters
- 11.4.3 Repeater Mode Timing Parameters
- 11.4.4 Transmit Packet Timing Parameters
- 11.4.5 Squelch Test Timing Parameters
- 11.4.6 Jabber Timing Parameters
- 11.4.7 Receive Packet Timing Parameters
- 11.4.8 10BASE-T Normal Link Pulse (NLP) Timing Parameters
- 11.4.9 Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters
- 11.4.10 Reset Timing Parameters
- 11.4.11 X1 Clock Specifications
- 11.4.12 100BASE-TX Transmitter AC Specification
- 12.0 82555 Package Information