Eurotech Appliances VIPER / VIPER-LITE PXA255 - Manual (Page 72)

VIPER Technical Manual Detailed hardware description
© 2007 Eurotech Ltd Issue E 72
JTAG and debug access
Debug access to the PXA255 processor is via the JTAG connector PL10. The
Macraigor
76H
Wiggler and EPI
77H
Majic MX probe have been used to debug the PXA255
processor on the VIPER. There are many other debug tools that can be interfaced to
the VIPER for access to the JTAG Interface of the PXA255 processor.
The tables below detail the pins connections between the VIPER and Macraigor
78H
Wiggler or EPI
79H
Majic MX debug tools. Of the
80H
Wiggler and
81H
Majic MX debug tools the
82H
Wiggler provides the best low cost solution.
VIPER JTAG connections
VIPER PL10 Debug tools pin names
Pin Name Description Majic MX Wiggler
1 VCC3 3.3V Supply pin to JTAG debug tool
VTRef,
VSupply Vref,
VTarget
3 GND Ground reference GND GND
4 nTRST PXA255 JTAG interface reset nTRST nTRST
6 TDI JTAG test data input to the PXA255 TDI TDI
7 TDO JTAG test data output from the PXA255 TDO TDO
8 TMS PXA255 JTAG test mode select TMS TMS
9 TCK PXA255 JTAG test clock TCK TCK
10 SRST System reset nSRST nSRST
2, 5 NC No Connect - -
- - Not required on VIPER. RTCLK RTCK
- - Not required on VIPER DBGREQ DBGRQ
- - Not supported by VIPER DBGACK DBGACK
In order to access the PXA255 your JTAG software needs to know the details
of the CPLD on the VIPER. The latest version of the ispMACH 4128C 100 Pin
TQFP BSDL file can be found on the
83H
Lattice Semiconductor web site.