Grass Valley 2010RDA - Manual (Page 24)

18 2010/2011RDA Instruction Manual
2010/2011RDA Dual/Quad AES/EBU Reclocking DA
AES Receivers
Each channel of AES3 audio is fed to the modules through an isolation
transformer into a crystal receiver IC where the data is reclocked by means
of a phase-locked-loop (PLL). Each AES Receiver controls the LOCK LEDs
which indicate when the receiver IC is locked to an incoming data stream.
The reclocked signal is then fed to the FPGA for routing and control.
Figure 15. 2010RDA-110/2011RDA-110 with 2000PRM-D
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FPGA
Routing and Control
Processor
2000PRM–D 2010RDA Module
AES Receiver
AES Receiver
Power Supply
Controller
J3
J1
CH 3 (2011RDA)
CH 4 (2011RDA)
LOCK 4 LED (2011RDA)
LOCK 3 LED (2011RDA)
AES Receiver CH 2
LOCK 2 LED
AES Receiver CH 1
LOCK 1 LED
FAULT LED
Configuration
Jumper
PWR LED
+5V
+3.3V
+24V
COMM LED
CONF LED
15-pin D-Connector
25-pin D-Connector
J2
25-pin D-Connector
Output
Driver
Output
Driver
Output
Driver
Output
Driver
Midplane