Adc chcd register 6 0x46, Adc chcd register 7 0x47 – Sundance SMT941 User Manual
Page 37

User Manual SMT941
Page 37 of 43
Last Edited: 23/08/2011 17:24:00
0
128 steps for a range of 0.134dB
ADC Chcd Register 6 0x46.
ADC Chcd Register 6 0x46
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Reserved
Test Patterns ChA
Default
‘00000’
‘000’
1
Reserved
Offset Pedestal ChA (Common)
Default
‘00’
ADC Chcd Register 6 0x46
Setting
Bit 2:0
Description Test Patterns ChA
0
‘000’
Normal Mode of Operation
1
‘001’
Outputs all zeroes
2
‘010’
Outputs all ones
3
‘011’
Outputs toggle pattern (0x1555 and 0x2AAA)
4
‘100’
Outputs digital ramp (0->16383)
5
‘101’
Outputs custom pattern
Setting
Bit 13:8
Description Offset Pedestal ChA (Common)
0
‘011111’
Pedestal=+31LSBs
1
‘011110’
Pedestal=+30LSBs
2
…
…
3
‘000000’
Pedestal=0
4
…
…
5
‘111111’
Pedestal=-1LSB
6
‘111110’
Pedestal=-2LSB
7
…
…
8
‘100000’
-32LSBs
ADC Chcd Register 7 0x47.
ADC Chcd Register 7 0x47
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Reserved
Offset
Correctio
n Enable
ChB
Reserved
Default
‘0’
‘0’
‘000000’
1
Gain ChB (Common)
Offset Correction Time Constant ChB
Default
‘0000’
‘0000’