Adc chcd register 0 0x40, Adc chcd register 1 0x41 – Sundance SMT941 User Manual
Page 33

User Manual SMT941
Page 33 of 43
Last Edited: 23/08/2011 17:24:00
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Reserved
Offset Pedestal ChB (Common)
Default
‘00’
1
Reserved
Default
‘00000000’
ADC Chab Register 9 0x39
Setting
Bit 5:0
Description Offset Pedestal ChA (Common)
0
‘011111’
Pedestal=+31LSBs
1
‘011110’
Pedestal=+30LSBs
2
…
…
3
‘000000’
Pedestal=0
4
…
…
5
‘111111’
Pedestal=-1LSB
6
‘111110’
Pedestal=-2LSB
7
…
…
8
‘100000’
-32LSBs
ADC Chcd Register 0 0x40.
ADC Chcd Register 0 0x40
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
Reserved
Enable Low
Speed
Mode
Reserved
Default
‘00000’
‘0’
‘00’
0
Software
Reset
Reserved
SerialRead
Out
Default
‘0’
‘000000’
‘0’
ADC Chcd Register 0 0x40
Setting
Bit 0
Description SerialReadOut
0
‘0’
Serial readout disabled.
1
‘1’
Serial readout enabled.
Setting
Bit 7
Description - Software Reset
0
‘0’
Normal mode of operation.
1
‘1’
Resets all internal registers and self-clears to ‘0’.
Setting
Bit 10
Description - Enable Low Speed Mode
0
‘0’
Low Speed Mode disabled. Sampling rates >100MSPS.
0
‘1’
Low Speed Mode enabled. Sampling rates <=100 MSPS.
ADC Chcd Register 1 0x41.