Sundance SMT941 - Manual (Page 13)

User Manual SMT941 Page 13 of 43 Last Edited: 23/08/2011 17:24:00
0x29 Clock Register 0x19. Read-back (FPGA Register) Clock Register 0x19.
0x2A Clock Readback Address Register (LSB)
0x2B Clock Readback Address Register (MSB)
ADCab Section
0x30 ADCab Register 0x0. Read-back (FPGA Register) ADCab Register 0x0.
0x31 ADCab Register 0x1. Read-back (FPGA Register) ADCab Register 0x1.
… ...
0x38 ADCab Register 0x8. Read-back (FPGA Register) ADCab Register 0x8.
0x39 ADCab Register 0x9. Read-back (FPGA Register) ADCab Register 0x9.
ADCcd Section
0x40 ADCcd Register 0x0. Read-back (FPGA Register) ADCcd Register 0x0.
0x41 ADCcd Register 0x1. Read-back (FPGA Register) ADCcd Register 0x1.
… ...
0x48 ADCcd Register 0x8. Read-back (FPGA Register) ADCcd Register 0x8.
0x49 ADCcd Register 0x9. Read-back (FPGA Register) ADCcd Register 0x9.
Figure 6 – Register Memory Map.
2.3.2 Register Descriptions
Control Register 0x1.
Control Register 0x01
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 Clk_Readb
ack
Default ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
0 Chcd
trigger
selection
Chdc
internal
trigger
Chab
trigger
selectio
n
Chab
internal
trigger
Chab reset Chcd
update
(dac)
Chab
update
(adc)
clk update
Default ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
Clock Register 0 0x10
Setting Bit 0 Description clk update clock chip register update
0 0 No action.
1 1 All clock registers are sent to the clock chip via its serial interface.
Setting Bit 1 Description chab update channel a and b register update
0 0 No action.
1 1 All registers (chab) are sent to the converter via its serial interface.
Setting Bit 2 Description chcd update channel c and d register update
0 1 No action.
1 1 All registers (chcd) are sent to the converter via its serial interface.
Setting Bit 4 Description chab Internal trigger
0 0 No action.
1 1 Starts the data flow (converter chab).