Sundance SMT911 User Manual
Page 36
SMT911 User Manual SMT911
Page 36 of 38
Last Edited: 01/06/2010 10:09:00
5
0
Dig Loop On. “0” = off; “1” = on (on only in full duplex mode)
4
0
SpiFDnHD. “0” = HD mode; “1” = FD mode
3
0
SpiTxnRx for toggling Tx & Rx in HD mode. “0” = Rx; “1” = Tx
2
0
SpiB10n20, option for 10 or 20 bit. “0” = 20-bit; “1” = 10-bit
1
0
SPI IO Control, in conjunction with Bit3 to override external TxnRx pin operation
0
0
SpiClone. “1” = for clone mode; “0” = other
This register is used for configuring the rest of the clock settings of ADDAC A.
Byte 1-0
D15 D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reconfigurable bits:
Bit
Default
Description
5
0
PLL to IFACE2. “0” = IFACE2 normal; “1” = IFACE2 switched to PLL output clock (FD)
2
0
PLL Slow. “0” = standard; “1” = changes phase noise generated from the PLL clock
Same settings as ADDAC A. See corresponding register.
Same settings as ADDAC A. See corresponding register.
Same settings as ADDAC A. See corresponding register.
Same settings as ADDAC A. See corresponding register.
Same settings as ADDAC A. See corresponding register.
Same settings as ADDAC A. See corresponding register.
Same settings as ADDAC A. See corresponding register.
Same settings as ADDAC A. See corresponding register.
Same settings as ADDAC A. See corresponding register.