Reconfigurable bits – Sundance SMT911 User Manual
Page 35
SMT911 User Manual SMT911
Page 35 of 38
Last Edited: 01/06/2010 10:09:00
Default
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Reconfigurable bits:
Bit
Default
Description
15
1
TxPGA Gain [7:0], is register control for the Tx programmable gain amplifier (TxPGA).
The TxPGA provides a 20 dB continuous gain range with 0.1 dB steps (linear in dB)
simultaneously to both Tx channels. Default is 0xFF.
“0000 0000” = Minimum gain scaling -20 dB
“1111 1111” = Maximum gain scaling 0dB
14
1
13
1
12
1
11
1
10
1
9
1
8
1
7
0
DAC B Coarse Gain Control. “00” = output current scaling by 1/11; “01” = output current
scaling by ½; “10” and “11” no output current scaling
6
0
5
0
DAC B Fine Gain [5:0] := “100000” Maximum positive gain adjustment;
“111111” Minimum positive gain adjustment;
“000000” default of no adjustment;
“000001” Minimum negative gain adjustment;
“011111” Maximum negative gain adjustment
4
0
3
0
2
0
1
0
0
0
This register is used for other settings of Tx Path and I/O configuration of ADDAC
A.
Byte 1-0
D15 D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reconfigurable bits:
Bit
Default
Description
15
0
Tx Twos Complement. “0” = straight binary; “1” = twos complement
14
0
Rx Twos Complement. “0” = straight binary; “1” = twos complement
13
0
Tx Inverse Sample. “0” = sampled on rising edge; “1” = sampled on falling edge clock
9
0
Interpolation control.
“00” = filters bypassed; “01” = interpolation rate 2x; “10” = interpolation rate 4x.
8
0
6
0
TxPGA Slave Enable. “0” = immediately after register updated; “1” = synchronized with
falling edge of a signal applied to the TxPwrDwn
4
0
TxPGA Fast Update. “0” = normal mode; “1” = fast mode
This register is used for I/O configuration and clock configuration of ADDAC A.
Byte 1-0
D15 D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reconfigurable bits:
Bit
Default
Description
15
0
PLL Bypass. “0” = PLL remains active; “1” = PLL bypassed
13
0
ADC Clock Div. “0” = no division; “1” = divides the clock by 2
12
0
Alt timing mode. “0” = normal timing operation; “1” = alternative operation mode
11
0
PLL Div5. “0” = no division; “1” = output of PLL divided by 5
10
0
PLL multiplication factor.
“000” = 1x; “001” = 2x; “010” = 4x; “011” = 8x; “100” = 16x; “101” ~ “111”: not used.
9
0
8
0