Sundance SMT911 - Manual (Page 28)

SMT911 User Manual SMT911 Page 28 of 38 Last Edited: 01/06/2010 10:09:00
This register contains the integer portion of the divider ratio of the synthesizer.
This register in conjunction with the fractional-divider ratio register, permits
selection of a precise frequency. Please refer to the appendix tables.
Byte 1-0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Default 0 0 1 1 0 0 0 0 1 0 1 0 0 0 1 1
Reconfigurable bits:
Bit
Default Description
13 1 2 LSBs of the Fractional-Divider Ratio
12 1
7 1 Integer-Divider Ratio Word Programming Bits. Valid values are from
128(Bit7:Bit0 = “10000000”) to 255 (Bit7:Bit0 = “11111111”) 6 0
5 1
4 0
3 0
2 0
1 1
0 0
This register (along with bit 13 and bit 12 of the integer divider ratio register)
controls the fractional-divider ratio with 16-bit resolution. Bit 13 to bit 0 of this
register combined with bit 13 and bit 12 of the integer-divider ratio register form
the whole fractional-divider ratio. To retain the complete frequency plan please
refer to the appendix tables.
Byte 1-0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Default 0 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1
Reconfigurable bits:
Bit
Default Description
13 0 Bit0:Bit13 = refer to Appendix : Frequency Plan and Divider Ratio Programming Words
12 1
11 1
10 1
9 1
8 1
7 1
6 1
5 0
4 1
3 1
2 1
1 0
0 1
This register configures the programmable-reference frequency dividers for the