Sundance SMT911 - Manual (Page 11)

SMT911 User Manual SMT911 Page 11 of 38 Last Edited: 01/06/2010 10:09:00
There are two MMCX connector clock inputs for the SMT911. Clock A provides a
40MHz clock input for the MAXIM transceiver IC‟s. Clock B is the input for both
CLKIN1 and CLKIN 2 of ADC/DAC A and ADC/DAC B. Clock distribution is achieved
by two CDCV304 clock buffer drivers. Because the clock inputs to both pins CLKIN1
and CLKIN2 of the ADC/DAC‟s are shared, the clock provided here cannot exceed
50MHz (the maximum speed of the internal ADC‟s) if switching from TX to RX is the
ultimate goal. To achieve higher frequencies with the DAC‟s, the ADC/DAC‟s
internal PLL circuitry must be implemented to multiply and output the clock onto
IFACE2. This is programmable via SPI up to 200MHz.
For ease of use, a high quality 40MHz crystal has been placed on the mezzanine to
provide clocking for either both MAXIM transceivers, both ADC/DAC‟s, or all four
IC‟s. These configurations are selectable via jumpers 1 and 2.
Jumper Both use XTAL Both use External XTAL CLKA/External CLKB External CLKA/XTAL CLKB
CLKA off on off on
CLKB off on on off
The clock source is driven by two jumper controlled, multi-function gates that drive
two CDCV304 clock buffers. The jumper marked CLKA will select the source clock
for the MAXIM chip. With no jumper, the defaulted clock source is the onboard
40MHz crystal. With the jumper, the external CLK6 jack (J6) is then the chosen input
for the MAXIM clock. The same arrangement exists for CLKB, the clock source for
the ADDAC chips. If the jumper is attached, an external clock source (J3) is
expected; otherwise, the crystal will output a 40MHz clock to pins CLKIN1 and
CLKIN2 of the ADDAC chips.
The external clock jacks are AC coupled and so do not require any DC offset to
drive this logic. The clock provided to the MAXIM chip if external must be 40MHz
from a quality, stable source. The clock provided to the ADC/DAC chips must be a
quality, clean source and not exceed 50MHz if in a switching TX/RX configuration,
as this source clock feeds the internal ADC and DAC.
A standard Xilinx parallel JTAG header is supplied on the mezzanine to provide access
to the base modules JTAG chain.