Reconfigurable bits – Sundance SMT911 User Manual
Page 34
SMT911 User Manual SMT911
Page 34 of 38
Last Edited: 01/06/2010 10:09:00
10
0
9
0
8
0
6
0
Rx Ultralow PowerControl. “0” = normal; “1” = set to Ultralow
5
0
Rx Ultralow PowerControl. “0” = normal; “1” = set to Ultralow
4
0
Rx Ultralow PowerControl. “0” = normal; “1” = set to Ultralow
This register is used for DAC A offset and DAC A gain control of ADDAC A.
Byte 1-0
D15 D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reconfigurable bits:
Bit
Default
Description
15
0
DAC A Coarse Gain Control. “00” = output current scaling by 1/11; “01” = output current
scaling by ½; “10” and “11” = no output current scaling
14
0
13
0
DAC A Fine Gain [5:0] := “100000” Maximum positive gain adjustment;
“111111” Minimum positive gain adjustment;
“000000” default of no adjustment;
“000001” Minimum negative gain adjustment;
“011111” Maximum negative gain adjustment
12
0
11
0
10
0
9
0
8
0
7
0
DAC A Offset [1:0]
6
0
0
0
DAC A Offset Direction. “0” = to negative diff. pin; “1” = to positive diff. pin
This register is used for DAC B offset and its direction of ADDAC A.
Byte 1-0
D15 D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reconfigurable bits:
Bit
Default
Description
15
0
DAC B Offset [1:0]
14
0
8
0
DAC B Offset Direction. “0” = to negative diff. pin; “1” = to positive diff. pin
7
0
DAC B Offset [9:2]
6
0
5
0
4
0
3
0
2
0
1
0
0
0
This register is used for DAC B offset gain control, fine gain, and TxPGA gain of
ADDAC A.
Byte 1-0
D15 D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0