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Version 1.0.0
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SMT407 User Manual
Table of Contents
Revision History ....................................................................................................... 2
Table of Contents ..................................................................................................... 3
Table of Figures........................................................................................................ 6
Table of Tables ......................................................................................................... 6
Physical Properties .................................................................................................. 7
Introduction............................................................................................................... 8
Related Documents ................................................................................................ 8
Block Diagram .......................................................................................................... 8
Mechanical Interface: PMC Standard...................................................................... 9
SMT407 Support ....................................................................................................... 9
SMT407 Installation .................................................................................................. 9
QL5064 .................................................................................................................... 11
Local bus............................................................................................................... 11
Virtex FPGA configuration..................................................................................... 11
Virtex FPGA design .............................................................................................. 12
TI JTAG controller ................................................................................................. 12
TMS320C6416T ....................................................................................................... 13
Boot Mode............................................................................................................. 13
EMIF Control Registers......................................................................................... 13
SDRAM ................................................................................................................. 14
FLASH .................................................................................................................. 14
Virtex FPGA .......................................................................................................... 15
FPGA ....................................................................................................................... 17
Configuration......................................................................................................... 17
JTAG/Boundary Scan........................................................................................ 17
Configuring with MultiLINX ................................................................................ 18
SHBs..................................................................................................................... 19
SHB Connectors................................................................................................ 19
SHB Cable Assembly ........................................................................................ 20
SHB Inter Modules solutions ............................................................................. 20
Half Word Interface (16-bit SHB Interface) ........................................................ 20
