Sundance SMT407 - Manual (Page 13)

Version 1.0.0 Page 13 of 38 SMT407 User Manual
TMS320C6416T
This section applies only to modules built with DSPs.
The processors will run with zero wait states from internal SRAM.
An on-board 50MHz crystal oscillator provides the clock used for the C60s which
then multiply this by 20 to achieve 1GHz internally.
Boot Mode
The SMT407 is configured to boot from Flash only after a reset.
Flash boot:
1. DSPA copies a bootstrap program from the first part of the flash memory into
internal program RAM starting at address 0.
2. Execution starts at address 0.
The standard bootstrap supplied with the SMT407 then performs the following
operations:
1. All relevant C60 internal registers are set to default values;
2. The FPGA is configured from data held in flash memory (DSPA only) and sets
up the communication ports, the global bus and the Sundance High-speed
Buses. This step must have been completed before data can be sent to the
Comports from external sources such as the host or other PMCs;
3. The same boot code is copied to DSPB over HPI and it repeats step 1.
4. A C4x-style boot loader is executed on DSPA and DSPB. This will continually
examine the communication ports until data appears on one of them. The
bootstrap will then load a program in boot format from that port; the loader will
not read data arriving on other ports.
5. Finally, control is passed to the loaded program.
The delay between the release of the board reset and the FPGA configuration is
around TBD s for a SMT407 (1GHz clock).
A typical time to wait after releasing the board reset should be in excess of this delay,
but no damage will result if any of the I/Os are used before they are fully configured.
In fact, the comm. Ports will just produce a not ready signal when data transfer is
attempted during this time, and then continue normally after the FPGA is configured.
EMIF Control Registers
The C6416 has two external memory interfaces (EMIFs). One of these is 64 bits
wide, the other 16 bits.