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Sundance SMT407 User Manual

Smt407, User manual

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User Manual; Version 1.0.2, 4/8/04; © Sundance Digital Signal Processing, Inc. 2004

SMT407

User Manual

Pages: 1 2 3 4 5 6 7 … 38

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Table of contents

Document Outline

Revision History
Table of Contents
Table of Figures
Table of Tables
Physical Properties
Introduction
- Related Documents
Block Diagram
Mechanical Interface: PMC Standard
SMT407 Support
SMT407 Installation
QL5064
- Local bus
- Virtex FPGA configuration
- Virtex FPGA design
- TI JTAG controller
TMS320C6416T
- Boot Mode
- EMIF Control Registers
- SDRAM
- FLASH
- Virtex FPGA
FPGA
- Configuration
  - JTAG/Boundary Scan
  - Configuring with MultiLINX
    - Using MultiLINX /Parallel cable III or IV
- SHBs
- RSLs
- Local bus
- Clocks
- Miscellaneous I/O
- Power Supplies
  - DC/DC converter
  - Linear Voltage regulator
- Power Consumption
FPDP
- Further details
Software
- Further details
Verification Procedures
Review Procedures
Validation Procedures
FPGA Constraint File General Information
Ordering Information
- FPGA-only
- With DSPs
- Custom
PCB Layout Details
- Components placement
Headers Pinout
- SHB Headers
  - SHB Pinout (LVTTL only) (J3,JA3)
- RSL Header
  - RSL Side 1 Pinout (LVDS only) (J2)
  - RSL Side 2 Pinout (LVDS only) (JA4)
- JTAG/Multilinx headers
  - JTAG Boundary scan pinout (J4)
- PMC Pn4 Header
  - PMC Pn4 Pinout (LVTTL only) (P14)
Safety
EMC

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