Sundance SMT407 - Manual (Page 29)

Version 1.0.0 Page 29 of 38 SMT407 User Manual
Verification Procedures
The specification (design requirements) will be tested using the following:
1) Power module test.
2) FPGA configuration using PCI and/or JTAG connector.
3) SDRAM memory tests.
4) SHB connector Pins Test using SHB tester PCBs.
5) PCI transfers between host and SMT407 FPGA.
Only for DSP boards:
Comport transfers between a host and the SMT407.
Review Procedures
Reviews will be carried out as indicated in design quality document QCF14 and in
accordance with Sundance’s ISO9000 procedures.
Validation Procedures
The validation procedure is happening during the verification procedure.
Test that all the memories are accessible by the FPGA as well as all the
communication links.
FPGA Constraint File General Information
Since only the FF1152 package type is supported on SMT407, one constraints file is
provided.
Ordering Information
Currently, the SMT407 is available in 2 configurations: FPGA-only and With DSPs.
FPGA-only
In the basic configuration a Virtex II Pro 50 is used and allows interfacing to ALL the
memories and ALL I/Os available on the SMT407. Two banks of 16MB of SDRAM
are installed attached to the FPGA.
With DSPs
This configuration includes everything in the FPGA-only variant with the addition of
two TI 6416T DSPs.