Sundance SMT407 - Manual (Page 17)

Version 1.0.0 Page 17 of 38 SMT407 User Manual
FPGA
The module can be fitted with an XC2VP20, XC2VP30, XC2VP40, or XC2VP50
FPGA.
Only flip-chip FF1152 package will fit on this board.
The choice of FPGA will be price/performance driven. The following table shows the
main FPGA characteristics.
The choice of the FPGA also determines which board architecture you will get
(amount of logic available, speed, number and type of I/Os, on-board Memory size
and type). For a complete list of the different board architectures, please consult:
Ordering Information
This Xilinx Virtex II Pro, is responsible for the provision of two SHBs, 4 internal
Comports (2 per DSP), a PCI Local bus interface, and 24 RSLs (In FULL
configuration, see Ordering Information).
CLB(1 CLB = 4 slices =
Max 128 bits)
SelectRAM Blocks Device
RocketIO
Transceiver
Blocks
PowerPC
Processor
Blocks
Logic
Cells
Slices
Maximum
distributed
RAM Kbits
Multiplier
blocks
18-Kbit
Block
Max RAM
(Kbits)
DCMs
XC2VP20 8 2 20,880 9,280 290 88 88 1,584 8
XC2VP30 8 2 30,816 13,696 428 136 136 2,448 8
XC2VP40 12 2 43,632 19,392 606 192 192 3,456 8
XC2VP50 16 2 53,136 23,616 738 232 232 4,176 8
Table 1: FPGA Choices
Configuration
The FPGA can be configured 3 different ways:
• Loading the FPGA from flash on the board using DSPA.
• Using SMT6041-407 to load the FPGA over the PCI bus.
• Using the on-board JTAG header and Xilinx JTAG programming tools.
JTAG/Boundary Scan
The JTAG Programmer software is a standard feature of the Alliance Series ™ and
Foundation Series ™ software packages. JTAG Programmer is a part of Web Pack,
which can be downloaded from the following site:
Xilinx JTAG programmer
The JTAG chain is composed only of the FPGA.