Sundance SMT381 2007 - Manual (Page 19)

connector. Used for verification of the clock going to the
DAC.
H J5 External RF clock input External Analog input Clock to DAC. Clock on inside of
connector, DGND on the outside of connector.
I J4 External ECL clock input External ECL input Clock to DAC. Positive on inside of
connector, negative on the outside of connector.
Table 2: Table of Connector Locations on SMT381
Diagram
Ref Pcb
RefDes Description Notes
J J8 FPGA / MSP JTAG
Connector FPGA / MSP430 on SMT338-VP JTAG Chain. Only
routed down to SMT338-VP. Use for easy access
without having to remove the SMT381.
K U9 Fujitsu DAC DAC Requires heat-sink with air-flow cooling in a
system setup.
L TRANS2 M/A Com TP101
Transformer By default the SMT381 analog input is AC coupled
through a twisted pair balum transformer
(differential to single ended). It is possible to change
this configuration to DC coupled by taking out the
transformer and inserting some resistors on the
board.
M TRANS1 M/A Com TP101
Transformer By default the SMT381 analog input is AC coupled
through a twisted pair balum transformer
(differential to single ended). It is possible to change
this configuration to DC coupled by taking out the
transformer and inserting some resistors on the
board.
N VCO1 UMC 600 – 1200MHz VCO System Clock for the DAC. VCO Requires heat-sink
with air-flow cooling in a system setup.
O U31 Clock Synthesizer 50 –
950MHz Test Clock for DAC. The range of this clock is wider
than the operating range of the DAC.
Table 3: Table of Component Locations on SMT381
6.2 Test points
The following diagram shows all the Test points present on the board.
User Manual SMT381 Page 19 of 31 Last Edited: 12/06/2007 10:43:00