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Table of Figures and Tables
Figure 1: Block Diagram................................................................................................................8
Figure 2:FPGA connections to Bank1 of ZBT...............................................................................9
Figure 3: ZBT Constraints file signal names ..............................................................................10
Figure 4: SHB Constraints file control signal names.................................................................10
Figure 5: SHB Constraints file data signal names ......................................................................11
Figure 6: ComPort Constraints file signal names ...................................................................... 12
Figure 7: Schematics of the External Clock I/O......................................................................... 13
Figure 8: CPLD state machine.................................................................................................... 14
Figure 9: PROM file selection..................................................................................................... 16
Figure 10: Program Options ....................................................................................................... 17
Figure 11: PROM programming..................................................................................................18
Figure 12: Programming succeeded ........................................................................................... 19
Figure 13: PCB – Top view......................................................................................................... 20
Figure 14: PCB – Bottom view.................................................................................................... 21
Figure 15: Pinout JTAG header – JP1 ........................................................................................22
Figure 16: Pinout JTAG header – JP1 ........................................................................................22
Figure 17: Boundary JTAG chain (Xilinx iMPACT)...................................................................23
Figure 18: Pinout TTL I/Os – JP3 ..............................................................................................23
Figure 19: Pinout TTL I/Os– JP3 ...............................................................................................23
Table 1: External Clock specification.......................................................................................... 12
Table 2: LEDs connections ......................................................................................................... 13
Table 3: SW1 DIP switch for the configuration mode selection ................................................ 14
Table 4: SW1 DIP switch for the configuration mode selection ................................................ 15
Table 5:SW2 DIP switch settings................................................................................................ 21
User Manual SMT368
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Last Edited: 31/12/2008 13:53:00
