Figure 15: pinout jtag header – jp1, Figure 16: pinout jtag header – jp1 – Sundance SMT368 User Manual
Page 22
Note: An adapter is necessary to connect the JTAG Header JP1 to the Xilinx
Parallel cable IV. Please ask your Sundance technical or sales person for
ordering information.
All devices from the Block_1 (FPGA, CPLD, PROM) are chained, and they are accessible via
this JTAG header.
Signal Pin Pin Signal
VCC 1 4 TMS
GND 2 5 TDI
TCK 3 6 TDO
Figure 15: Pinout JTAG header – JP1
Figure 16: Pinout JTAG header – JP1
User Manual SMT368
Page 22 of 24
Last Edited: 31/12/2008 13:53:00
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