Sundance SMT368 - Manual (Page 21)

Sundance Multiprocessor Technology Limited
Form : QCF42
User Manual
Date : 6 July 2006
5.2 Bottom View
Figure 14: PCB – Bottom view
6 Pinout
6.1 DIP switch SW2
The DIP switch SW2 is not used in the default firmware. It is therefore connected to the
CPLD for custom applications.
The following table describes the settings for the positions of the SW2:
Configuration
SW2 Pos POS1 POS2 POS3 POS4
Pin of CPLD 53 52 51 50
Type I/O I/O I/O I/O
Table 5:SW2 DIP switch settings
6.2 SHB Header
The SHB connectors support LVTTL standard only. They are referenced SHBA, SHBB, SHBC
and SHBD.
6.3 JTAG Header
The JTAG header is a 2mm pitch pin-socket, and it is referenced JP1. It is compliant with the
Xilinx Parallel cable IV .
User Manual SMT368 Last Edited: 31/12/2008 13:53:00