Sundance SMT368 - Manual (Page 11)

Figure 5: SHB Constraints file data signal names
4.1.8 Sundance Low voltage differential signals Bus
1 x 60 LVDS pairs I/O connections between the FPGA and the outside world.
They allow interfacing to the Sundance mezzanine modules by implementing a SLB interface
in the FPGA.
Sundance provides the interfaces to the mezzanines supported on this module.
For the mezzanines supported, please contact Sundance technical support, as
more mezzanines are supported over time.
They allow interfacing to the outside world by implementing your own LVDS interface in the
FPGA.
The FPGA I/O banks hosting the SLB signals are powered using Vcco=2.5V.
User Manual SMT368 Page 11 of 24 Last Edited: 31/12/2008 13:53:00