Sundance SMT300Q v.1.6 - Manual (Page 41)

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
14.2 CompactPCI-To-SMT300Q Interrupts
TIMIIOF0
TIMIIOF1
TIMIIOF2
CONTROL
REGISTER
CONTROL CPLD
LINT LINT
LINT can
be caused
by any PCI
interrupt
e.g. Mailbox
IIOF0
IIOF1
IIOF2
PCI
Bridge
INTREG
REGISTER
TIMIIOF0 IE
TIMIIOF1 IE
TIMIIOF2 IE
Figure 11 : CompactPCI to SMT300Q Interrupts
14.3 Interrupt Registers
The following register are used to control CompactPCI-To-DSP and DSP-To-
CompactPCI interrupts:
Note that Control Register (Offset 0x14, BAR1) and Interrupt Control Register (Offset
0x18, BAR1) are also used to control interrupts.
14.3.1 CompactPCI Interrupt Configuration Register(Offset 0x4C, BAR0)
Bits Name Description
31 MAILBOX Mailbox Interrupt Enable: Enables a CompactPCI interrupt
from the mailbox unit
30 LOCAL Local Bus Direct Interrupt Enable: Enables direct local bus
to CompactPCI interrupts
29 MASTER_PI CompactPCI Master Local Interrupt Enable: (see V3
datasheet)
28 SLAVE_PI CompactPCI Slave Local Interrupt Enable: (see V3
datasheet)
27 OUT-POST I2O Outbound Post List Not Empty: (see V3 datasheet)