Sundance SMT300Q v.1.6 User Manual

Page 24

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999

8.3 Status Register (Offset 0x14, BAR1 , Read-Only)

OBE IE

Set if ComPort output buffer empty interrupts enabled.

IBF IE

Set if ComPort input buffer full interrupts enabled

TBC IE

Set if JTAG interrupts enabled

C40 IE

Set if interrupt from TIM DSP enabled

OBE INT

Set if the ComPort output buffer becomes empty. Cleared by writing a
1 to the corresponding bit in the interrupt control register.

IBF INT

Set if the ComPort input buffer receives a word. Cleared by writing a
1to the corresponding bit in the interrupt control register

TBC INT

Set when the TBC asserts its interrupt. Cleared by removing the
source of the interrupt in the TBC.

C40 INT

Set when the TIM DSP sets its host interrupt bit. Cleared by writing a
1 to the corresponding bit in the interrupt control register.

INTD

The logical OR of bits 7—4 in this register gated with each one’s
enable bit.

OBF

Set when a word is written to the ComPort output register. Cleared
when the word has been transmitted to the DSP.

IM0

Interrupt mask 0. Returns Interrupt Control Register Bit 8.

IM1

Interrupt mask 1. Returns Interrupt Control Register Bit 9.

IM2

Interrupt mask 2. Returns Interrupt Control Register Bit 10.

IBF

Set when a word is in the ComPort input register.

MASTER

Set when the SMT300Q bridge owns the ComPort interface token.

TBC RDY

Reflects the current state of the TBC RDY pin. This bit is active high
and therefore and inversion of the TBC pin.

CONFIG_L

Reflects the state of the TIMs’ CONFIG signal. Active low.

Table 16 : Status Register

INTD is the input interrupt into the CompactPCI Bridge from the SMT300Q, this can

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