Sundance SMT300Q v.1.6 User Manual
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SMT300Q SMT300Q User Guide V1.65
be routed to either INTA, INTB, or INTC using the CompactPCI Interrupt
Configuration Register (offset 0x4C, BAR0)
8.4 Interrupt Control Register (Offset 0x18, BAR1)
This write-only register controls the generation of interrupts on the CompactPCI bus.
Each interrupt source has an associated enable and clear flag. This register can be
written with the contents of bits 7:0 of the Status Register.
10
9
DSP-PC IIOF2 En
DSP-PC IIOF1 En
8
7
6
5
4
3
2
1
0
DSP-PC
IIOF0 En
CLEAR
C40 INT
0 CLEAR
IBF INT
CLEAR OBE
INT
C40 IE
TBC IE
IBF IE
OBE IE
DSP-PC IIOF2 En
Enables DSP-PC interrupts on IIOF2
DSP-PC IIOF1 En
Enables DSP-PC interrupts on IIOF1
DSP-PC IIOF0 En
Enables DSP-PC interrupts on IIOF0
IBF
IE
ComPort Input Buffer Full Interrupt Enable. Allows an
interrupt to be generated when the host ComPort input
register is loaded with data from the C40.
OBE IE
ComPort Output Buffer Empty Interrupt. Allows an interrupt to
be generated when the host ComPort register has transmitted
its contents.
TBC IE
Test Bus Controller Interrupt Enable. Interrupts from the
Texas JTAG controller are enabled when set.
C40 IE
C40 Interrupt Enable. Allows a programmed interrupt to be
generated by the C40 when set.
CLEAR OBE INT
Write a one to this bit to clear the interrupt resulting from a
ComPort output event.
CLEAR IBF INT
Write a one to this bit to clear the interrupt event resulting
from ComPort input.
CLEAR C40 INT
Write a one to this bit to clear down the C40 INT event.
Table 17 : Interrupt Control Register
The JTAG controller, which generates TBC INT, must be cleared of all interrupt
sources in order to clear the interrupt.