Sundance SMT300Q v.1.6 - Manual (Page 37)

Page 37 of 61 SMT300Q SMT300Q User Guide V1.65
mode. This interface allows a synchronous stream of data to be written to the 256
WORD input FIFO of the Local To CompactPCI aperture 0. For more information on
setting this mode from the DSP can be found in the SMT335 Users Guide. This
section concentrates on the burst mode interface and arbitration mechanism for the
DSP to CompactPCI Bridge aperture access.
The Global bus interface of the DSP uses the following signals to interface to the
local bus of the SMT300Q.
DSP Signals.
AE*, DE*, CE0*
AE*/DE* are active low address/Data enable signal driven by the SMT300Q, when
the DSP has ownership of the Bus this signal is driven low by the SMT300Q allowing
the DSP to drive the Address pins and Data pins.
CE0* is the Tri-state control for the DSP’s global bus control pins. This is permanently
tied low by the SMT300Q as the control signals are always enable.
STRB1*
This is the data strobe signal from the DSP’s global bus. It is driven low when the
DSP is carrying out an access cycle. The DSP waits for the RDY1* to be driven low
by the SMT300Q to indicate transfer has been completed. This transfer is carried out
in synchronous burst mode. The DSP signals when the burst transfer is completed
by pulling STAT0 low.
RDY1*
This is an active low transfer acknowledgement, driven by the SMT300Q to indicate
that the current transfer has been completed.
STAT0..STAT3
These comprise the DSP Status line. When all of the signals are logic ‘1’ then the
DSP Global bus interface is in an idle state. When any of these signals is driven low
the DSP is requesting ownership of the SMT300Q’s local bus. STAT0 has a special
meaning and is driven low by the DSP to indicate the last data packet transfer.