Sundance SMT300Q v.1.6 - Manual (Page 34)

Page 34 of 61 SMT300Q SMT300Q User Guide V1.65
The mailbox registers themselves are on byte boundaries with offsets 0xC0 -> 0xCF,
from the LB_IO_BASE. As DSP global bus accesses are carried out on WORD (32-
bit) boundaries a write access over the global bus to 0x1C00 0000 + 0xC0 will write
to the first 4 mailbox registers in the CompactPCI Bridge device.
The mailbox registers are accessed from the CompactPCI bus through the
CompactPCI-to-Internal Register (CompactPCI_IO_BASE) aperture. This is
accessed via the CompactPCI Bridge Chip Internal Register (BAR0), byte offset
0xC0 -> 0xCF.
13.1.1 Doorbell Interrupts
Each of the 16 mailbox registers can generate four different interrupt requests called
doorbell interrupts. Each of these requests can be independently masked for each
mailbox register. The four doorbell interrupt types are:
• DSP interrupt request on read from CompactPCI side
• DSP interrupt request on write from CompactPCI side
• CompactPCI interrupt request on read from DSP side
• CompactPCI interrupt request on write from DSP side
The CompactPCI read and DSP read interrupts are OR’d together and latched in the
mailbox read interrupt status register (MAIL_RD_STAT). Similarly, the CompactPCI
write and DSP write interrupts are OR’d together and latched in the mailbox write
interrupt status register (MAIL_WR_STAT). All of the interrupt request outputs from
the status registers are OR’d together to form a single mailbox unit interrupt request
and routed to both the Local and CompactPCI Interrupt Control Units.
When a block of mailbox registers are accessed simultaneously, for example when 4
mailbox registers are read as a word quantity, then each register affected will request
a separate interrupt if programmed to do so.
See section 14 for further information on Interrupts.
13.2 DSP Interrupt Control
Interrupts can be enabled from a number of different sources i.e. DSP-> Host and
Host -> DSP. See section 14 for a description of these functions.